returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.\r
+ /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
///\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:2;\r
///\r
/// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2. Default value is 1.\r
+ /// Table 2-2. Default value is 1.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
- /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.\r
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
///\r
UINT32 PerformanceMonitoring:1;\r
UINT32 Reserved3:3;\r
///\r
- /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
UINT32 BTS:1;\r
///\r
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved4:3;\r
///\r
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 EIST:1;\r
UINT32 Reserved5:1;\r
///\r
- /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
UINT32 MONITOR:1;\r
UINT32 Reserved6:3;\r
///\r
- /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.\r
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
///\r
- /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 35-2.\r
+ /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
UINT32 xTPR_Message_Disable:1;\r
UINT32 Reserved7:8;\r
UINT32 Reserved8:2;\r
///\r
- /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.\r
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
///\r
UINT32 XD:1;\r
UINT32 Reserved9:3;\r
\r
\r
/**\r
- Core. Last Branch Record Filtering Select Register (R/W) See Section\r
- 17.7.2, "Filtering of Last Branch Records.".\r
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
+ "Filtering of Last Branch Records.".\r
\r
@param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of\r
- an 128-bit external entropy value for key derivation of an enclave.\r
+ Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
+ the package. Lower 64 bits of an 128-bit external entropy value for key\r
+ derivation of an enclave.\r
\r
- @param ECX MSR_GOLDMONT_SGXOWNER0 (0x00000300)\r
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER0);\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);\r
@endcode\r
- @note MSR_GOLDMONT_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.\r
+ @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.\r
**/\r
-#define MSR_GOLDMONT_SGXOWNER0 0x00000300\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r
+\r
+\r
+//\r
+// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.\r
+//\r
+#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r
\r
\r
/**\r
Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r
an 128-bit external entropy value for key derivation of an enclave.\r
\r
- @param ECX MSR_GOLDMONT_SGXOWNER1 (0x00000301)\r
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER1);\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);\r
@endcode\r
- @note MSR_GOLDMONT_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.\r
+ @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.\r
**/\r
-#define MSR_GOLDMONT_SGXOWNER1 0x00000301\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r
+\r
+\r
+//\r
+// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.\r
+//\r
+#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r
\r
\r
/**\r
- Core. See Table 35-2. See Section 18.2.4, "Architectural Performance\r
+ Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
Monitoring Version 4.".\r
\r
@param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
\r
\r
/**\r
- Core. See Table 35-2. See Section 18.2.4, "Architectural Performance\r
+ Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
Monitoring Version 4.".\r
\r
@param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
\r
\r
/**\r
- Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
+ Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)\r
///\r
UINT32 InterruptResponseTimeLimit:10;\r
///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. See Table 35-18 for\r
- /// supported time unit encodings.\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
///\r
UINT32 TimeUnit:3;\r
UINT32 Reserved1:2;\r
///\r
UINT32 InterruptResponseTimeLimit:10;\r
///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. See Table 35-18 for\r
- /// supported time unit encodings.\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
///\r
UINT32 TimeUnit:3;\r
UINT32 Reserved1:2;\r
///\r
UINT32 InterruptResponseTimeLimit:10;\r
///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. See Table 35-18 for\r
- /// supported time unit encodings.\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
///\r
UINT32 TimeUnit:3;\r
UINT32 Reserved1:2;\r
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