returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Is Intel processors based on the Haswell-E microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x3F \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Package. Configured State of Enabled Processor Core Count and Logical\r
+ Processor Count (RO) - After a Power-On RESET, enumerates factory\r
+ configuration of the number of processor cores and logical processors in the\r
+ physical package. - Following the sequence of (i) BIOS modified a\r
+ Configuration Mask which selects a subset of processor cores to be active\r
+ post RESET and (ii) a RESET event after the modification, enumerates the\r
+ current configuration of enabled processor core count and logical processor\r
+ count in the physical package.\r
+\r
+ @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);\r
+ @endcode\r
+ @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r
+**/\r
+#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are\r
+ /// currently enabled (by either factory configuration or BIOS\r
+ /// configuration) in the physical package.\r
+ ///\r
+ UINT32 Core_Count:16;\r
+ ///\r
+ /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r
+ /// are currently enabled (by either factory configuration or BIOS\r
+ /// configuration) in the physical package.\r
+ ///\r
+ UINT32 Thread_Count:16;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. A Hardware Assigned ID for the Logical Processor (RO).\r
+\r
+ @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);\r
+ @endcode\r
+ @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r
+**/\r
+#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific\r
+ /// numerical. value physically assigned to each logical processor. This\r
+ /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r
+ /// a physical package.\r
+ ///\r
+ UINT32 Logical_Processor_ID:8;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r
+\r
+\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
\r
\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- * Bank MC5 reports MC error from the Intel QPI 0 module.\r
- * Bank MC6 reports MC error from the integrated I/O module.\r
- * Bank MC7 reports MC error from the home agent HA 0.\r
- * Bank MC8 reports MC error from the home agent HA 1.\r
- * Banks MC9 through MC16 report MC error from each channel of the integrated\r
- memory controllers.\r
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
- * Bank MC20 reports MC error from the Intel QPI 1 module.\r
- * Bank MC21 reports MC error from the Intel QPI 2 module.\r
-\r
- @param ECX MSR_HASWELL_E_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_HASWELL_E_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_HASWELL_E_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_HASWELL_E_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_HASWELL_E_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
- MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_CTL 0x00000414\r
-#define MSR_HASWELL_E_MC6_CTL 0x00000418\r
-#define MSR_HASWELL_E_MC7_CTL 0x0000041C\r
-#define MSR_HASWELL_E_MC8_CTL 0x00000420\r
-#define MSR_HASWELL_E_MC9_CTL 0x00000424\r
-#define MSR_HASWELL_E_MC10_CTL 0x00000428\r
-#define MSR_HASWELL_E_MC11_CTL 0x0000042C\r
-#define MSR_HASWELL_E_MC12_CTL 0x00000430\r
-#define MSR_HASWELL_E_MC13_CTL 0x00000434\r
-#define MSR_HASWELL_E_MC14_CTL 0x00000438\r
-#define MSR_HASWELL_E_MC15_CTL 0x0000043C\r
-#define MSR_HASWELL_E_MC16_CTL 0x00000440\r
-#define MSR_HASWELL_E_MC17_CTL 0x00000444\r
-#define MSR_HASWELL_E_MC18_CTL 0x00000448\r
-#define MSR_HASWELL_E_MC19_CTL 0x0000044C\r
-#define MSR_HASWELL_E_MC20_CTL 0x00000450\r
-#define MSR_HASWELL_E_MC21_CTL 0x00000454\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_HASWELL_E_MCi_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_HASWELL_E_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_HASWELL_E_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_HASWELL_E_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_HASWELL_E_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_HASWELL_E_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_HASWELL_E_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_HASWELL_E_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- MSR_HASWELL_E_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
- MSR_HASWELL_E_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_STATUS 0x00000415\r
-#define MSR_HASWELL_E_MC6_STATUS 0x00000419\r
-#define MSR_HASWELL_E_MC7_STATUS 0x0000041D\r
-#define MSR_HASWELL_E_MC8_STATUS 0x00000421\r
-#define MSR_HASWELL_E_MC9_STATUS 0x00000425\r
-#define MSR_HASWELL_E_MC10_STATUS 0x00000429\r
-#define MSR_HASWELL_E_MC11_STATUS 0x0000042D\r
-#define MSR_HASWELL_E_MC12_STATUS 0x00000431\r
-#define MSR_HASWELL_E_MC13_STATUS 0x00000435\r
-#define MSR_HASWELL_E_MC14_STATUS 0x00000439\r
-#define MSR_HASWELL_E_MC15_STATUS 0x0000043D\r
-#define MSR_HASWELL_E_MC16_STATUS 0x00000441\r
-#define MSR_HASWELL_E_MC17_STATUS 0x00000445\r
-#define MSR_HASWELL_E_MC18_STATUS 0x00000449\r
-#define MSR_HASWELL_E_MC19_STATUS 0x0000044D\r
-#define MSR_HASWELL_E_MC20_STATUS 0x00000451\r
-#define MSR_HASWELL_E_MC21_STATUS 0x00000455\r
-/// @}\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_HASWELL_E_MCi_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_HASWELL_E_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_HASWELL_E_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_HASWELL_E_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_HASWELL_E_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_HASWELL_E_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_HASWELL_E_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_HASWELL_E_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_HASWELL_E_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_HASWELL_E_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_HASWELL_E_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_HASWELL_E_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_HASWELL_E_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_HASWELL_E_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_HASWELL_E_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- MSR_HASWELL_E_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
- MSR_HASWELL_E_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_ADDR 0x00000416\r
-#define MSR_HASWELL_E_MC6_ADDR 0x0000041A\r
-#define MSR_HASWELL_E_MC7_ADDR 0x0000041E\r
-#define MSR_HASWELL_E_MC8_ADDR 0x00000422\r
-#define MSR_HASWELL_E_MC9_ADDR 0x00000426\r
-#define MSR_HASWELL_E_MC10_ADDR 0x0000042A\r
-#define MSR_HASWELL_E_MC11_ADDR 0x0000042E\r
-#define MSR_HASWELL_E_MC12_ADDR 0x00000432\r
-#define MSR_HASWELL_E_MC13_ADDR 0x00000436\r
-#define MSR_HASWELL_E_MC14_ADDR 0x0000043A\r
-#define MSR_HASWELL_E_MC15_ADDR 0x0000043E\r
-#define MSR_HASWELL_E_MC16_ADDR 0x00000442\r
-#define MSR_HASWELL_E_MC17_ADDR 0x00000446\r
-#define MSR_HASWELL_E_MC18_ADDR 0x0000044A\r
-#define MSR_HASWELL_E_MC19_ADDR 0x0000044E\r
-#define MSR_HASWELL_E_MC20_ADDR 0x00000452\r
-#define MSR_HASWELL_E_MC21_ADDR 0x00000456\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_HASWELL_E_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_HASWELL_E_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_HASWELL_E_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_HASWELL_E_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_HASWELL_E_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_HASWELL_E_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_HASWELL_E_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_HASWELL_E_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_HASWELL_E_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_HASWELL_E_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_HASWELL_E_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_HASWELL_E_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_HASWELL_E_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_HASWELL_E_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_HASWELL_E_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- MSR_HASWELL_E_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
- MSR_HASWELL_E_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_MISC 0x00000417\r
-#define MSR_HASWELL_E_MC6_MISC 0x0000041B\r
-#define MSR_HASWELL_E_MC7_MISC 0x0000041F\r
-#define MSR_HASWELL_E_MC8_MISC 0x00000423\r
-#define MSR_HASWELL_E_MC9_MISC 0x00000427\r
-#define MSR_HASWELL_E_MC10_MISC 0x0000042B\r
-#define MSR_HASWELL_E_MC11_MISC 0x0000042F\r
-#define MSR_HASWELL_E_MC12_MISC 0x00000433\r
-#define MSR_HASWELL_E_MC13_MISC 0x00000437\r
-#define MSR_HASWELL_E_MC14_MISC 0x0000043B\r
-#define MSR_HASWELL_E_MC15_MISC 0x0000043F\r
-#define MSR_HASWELL_E_MC16_MISC 0x00000443\r
-#define MSR_HASWELL_E_MC17_MISC 0x00000447\r
-#define MSR_HASWELL_E_MC18_MISC 0x0000044B\r
-#define MSR_HASWELL_E_MC19_MISC 0x0000044F\r
-#define MSR_HASWELL_E_MC20_MISC 0x00000453\r
-#define MSR_HASWELL_E_MC21_MISC 0x00000457\r
-/// @}\r
-\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
\r
\r
\r
/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+ Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.\r
\r
@param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r
@param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
@endcode\r
@note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
\r
\r
+/**\r
+ Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r
+\r
+ @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz\r
+ /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use\r
+ /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r
+ /// operation.\r
+ ///\r
+ UINT32 PCIERatio:2;\r
+ ///\r
+ /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r
+ /// PCIE Ratio.\r
+ ///\r
+ UINT32 LPLLSelect:1;\r
+ ///\r
+ /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r
+ /// before re-locking Gen2/Gen3 PLLs.\r
+ ///\r
+ UINT32 LONGRESET:1;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
refers to processor core frequency).\r
\r
/**\r
THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
- ECX=0):EBX.PQM[bit 12] = 1.\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
\r
@param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r
@param EAX Lower 32-bits of MSR value.\r
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