returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.4.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Is Intel processors based on the Silvermont microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x37 || \\r
+ DisplayModel == 0x4A || \\r
+ DisplayModel == 0x4D || \\r
+ DisplayModel == 0x5A || \\r
+ DisplayModel == 0x5D \\r
+ ) \\r
+ )\r
+\r
/**\r
Module. Model Specific Platform ID (R).\r
\r
UINT32 Reserved2:19;\r
UINT32 Reserved3:18;\r
///\r
- /// [Bits 52:50] See Table 35-2.\r
+ /// [Bits 52:50] See Table 2-2.\r
///\r
UINT32 PlatformId:3;\r
UINT32 Reserved4:11;\r
\r
\r
/**\r
- Core. Control Features in Intel 64 Processor (R/W). See Table 35-2.\r
+ Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.\r
\r
@param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)\r
@param EAX Lower 32-bits of MSR value.\r
} MSR_SILVERMONT_FSB_FREQ_REGISTER;\r
\r
\r
+/**\r
+ Package. Platform Information: Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio\r
+ /// of the maximum frequency that does not require turbo. Frequency =\r
+ /// ratio * Scalable Bus Frequency.\r
+ ///\r
+ UINT32 MaximumNon_TurboRatio:8;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;\r
+\r
/**\r
Module. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
///\r
struct {\r
///\r
- /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.\r
+ /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
///\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:2;\r
///\r
/// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2. Default value is 0.\r
+ /// Table 2-2. Default value is 0.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
- /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.\r
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
///\r
UINT32 PerformanceMonitoring:1;\r
UINT32 Reserved3:3;\r
///\r
- /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
UINT32 BTS:1;\r
///\r
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved4:3;\r
///\r
/// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 EIST:1;\r
UINT32 Reserved5:1;\r
///\r
- /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
UINT32 MONITOR:1;\r
UINT32 Reserved6:3;\r
///\r
- /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.\r
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
///\r
- /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 35-2.\r
+ /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
UINT32 xTPR_Message_Disable:1;\r
UINT32 Reserved7:8;\r
UINT32 Reserved8:2;\r
///\r
- /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.\r
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
///\r
UINT32 XD:1;\r
UINT32 Reserved9:3;\r
\r
\r
/**\r
- Core. Last Branch Record Filtering Select Register (R/W) See Section\r
- 17.7.2, "Filtering of Last Branch Records.".\r
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
+ "Filtering of Last Branch Records.".\r
\r
@param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
+ Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)\r
\r
\r
/**\r
- Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
+ Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
\r
@param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Core. Capability Reporting Register of VM-function Controls (R/O) See Table\r
- 35-2.\r
+ Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
+ 2-2.\r
\r
@param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package\r
- /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
+ /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package\r
+ /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.\r
///\r
UINT32 Limit:15;\r
///\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r
- and MSR_RAPL_POWER_UNIT in Table 35-8.\r
+ and MSR_RAPL_POWER_UNIT in Table 2-8.\r
\r
@param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."\r
+ and MSR_RAPL_POWER_UNIT in Table 2-8.\r
\r
@param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)\r
@param EAX Lower 32-bits of MSR value.\r
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