returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Is Intel(R) Xeon(R) Processor D product Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x4F || \\r
+ DisplayModel == 0x56 \\r
+ ) \\r
+ )\r
+\r
/**\r
Package. Protected Processor Inventory Number Enable Control (R/W).\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] LockOut (R/WO) See Table 35-21.\r
+ /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
///\r
UINT32 LockOut:1;\r
///\r
- /// [Bit 1] Enable_PPIN (R/W) See Table 35-21.\r
+ /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
///\r
UINT32 Enable_PPIN:1;\r
UINT32 Reserved1:30;\r
\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
- Inventory Number (R/O) See Table 35-21.\r
+ Inventory Number (R/O) See Table 2-25.\r
\r
@param ECX MSR_XEON_D_PPIN (0x0000004F)\r
@param EAX Lower 32-bits of MSR value.\r
struct {\r
UINT32 Reserved1:8;\r
///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
///\r
UINT32 MaximumNonTurboRatio:8;\r
UINT32 Reserved2:7;\r
///\r
- /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.\r
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
///\r
UINT32 PPIN_CAP:1;\r
UINT32 Reserved3:4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
- /// Table 35-21.\r
+ /// Table 2-25.\r
///\r
UINT32 RatioLimit:1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
- /// Table 35-21.\r
+ /// Table 2-25.\r
///\r
UINT32 TDPLimit:1;\r
///\r
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
///\r
UINT32 TJOFFSET:1;\r
UINT32 Reserved4:1;\r
UINT32 Reserved5:8;\r
///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-21.\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
///\r
UINT32 MaximumEfficiencyRatio:8;\r
UINT32 Reserved6:16;\r
struct {\r
UINT32 Reserved1:16;\r
///\r
- /// [Bits 23:16] Temperature Target (RO) See Table 35-21.\r
+ /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
///\r
UINT32 TemperatureTarget:8;\r
///\r
- /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-21.\r
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
///\r
UINT32 TCCActivationOffset:4;\r
UINT32 Reserved2:4;\r
\r
\r
/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+ Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
\r
@param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
@param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
@endcode\r
@note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
\r
\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
refers to processor core frequency).\r
\r
/**\r
THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
- ECX=0):EBX.PQM[bit 12] = 1.\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
\r
@param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
@param EAX Lower 32-bits of MSR value.\r
} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
\r
\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- * Bank MC5 reports MC error from the Intel QPI 0 module.\r
- * Bank MC6 reports MC error from the integrated I/O module.\r
- * Bank MC7 reports MC error from the home agent HA 0.\r
- * Bank MC8 reports MC error from the home agent HA 1.\r
- * Banks MC9 through MC16 report MC error from each channel of the integrated\r
- memory controllers.\r
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
- * Bank MC20 reports MC error from the Intel QPI 1 module.\r
- * Bank MC21 reports MC error from the Intel QPI 2 module.\r
-\r
- @param ECX MSR_XEON_D_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);\r
- AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_XEON_D_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_XEON_D_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_XEON_D_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_XEON_D_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_XEON_D_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_XEON_D_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_XEON_D_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_XEON_D_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_XEON_D_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_XEON_D_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_XEON_D_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_XEON_D_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_XEON_D_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_XEON_D_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- MSR_XEON_D_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
- MSR_XEON_D_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_CTL 0x00000414\r
-#define MSR_XEON_D_MC6_CTL 0x00000418\r
-#define MSR_XEON_D_MC7_CTL 0x0000041C\r
-#define MSR_XEON_D_MC8_CTL 0x00000420\r
-#define MSR_XEON_D_MC9_CTL 0x00000424\r
-#define MSR_XEON_D_MC10_CTL 0x00000428\r
-#define MSR_XEON_D_MC11_CTL 0x0000042C\r
-#define MSR_XEON_D_MC12_CTL 0x00000430\r
-#define MSR_XEON_D_MC13_CTL 0x00000434\r
-#define MSR_XEON_D_MC14_CTL 0x00000438\r
-#define MSR_XEON_D_MC15_CTL 0x0000043C\r
-#define MSR_XEON_D_MC16_CTL 0x00000440\r
-#define MSR_XEON_D_MC17_CTL 0x00000444\r
-#define MSR_XEON_D_MC18_CTL 0x00000448\r
-#define MSR_XEON_D_MC19_CTL 0x0000044C\r
-#define MSR_XEON_D_MC20_CTL 0x00000450\r
-#define MSR_XEON_D_MC21_CTL 0x00000454\r
-/// @}\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_XEON_D_MCi_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_XEON_D_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_XEON_D_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_XEON_D_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_XEON_D_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_XEON_D_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_XEON_D_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_XEON_D_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_XEON_D_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_XEON_D_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_XEON_D_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_XEON_D_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_XEON_D_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_XEON_D_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_XEON_D_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- MSR_XEON_D_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
- MSR_XEON_D_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_STATUS 0x00000415\r
-#define MSR_XEON_D_MC6_STATUS 0x00000419\r
-#define MSR_XEON_D_MC7_STATUS 0x0000041D\r
-#define MSR_XEON_D_MC8_STATUS 0x00000421\r
-#define MSR_XEON_D_MC9_STATUS 0x00000425\r
-#define MSR_XEON_D_MC10_STATUS 0x00000429\r
-#define MSR_XEON_D_MC11_STATUS 0x0000042D\r
-#define MSR_XEON_D_MC12_STATUS 0x00000431\r
-#define MSR_XEON_D_MC13_STATUS 0x00000435\r
-#define MSR_XEON_D_MC14_STATUS 0x00000439\r
-#define MSR_XEON_D_MC15_STATUS 0x0000043D\r
-#define MSR_XEON_D_MC16_STATUS 0x00000441\r
-#define MSR_XEON_D_MC17_STATUS 0x00000445\r
-#define MSR_XEON_D_MC18_STATUS 0x00000449\r
-#define MSR_XEON_D_MC19_STATUS 0x0000044D\r
-#define MSR_XEON_D_MC20_STATUS 0x00000451\r
-#define MSR_XEON_D_MC21_STATUS 0x00000455\r
-/// @}\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_XEON_D_MCi_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_XEON_D_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_XEON_D_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_XEON_D_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_XEON_D_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_XEON_D_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_XEON_D_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_XEON_D_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_XEON_D_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_XEON_D_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_XEON_D_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_XEON_D_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_XEON_D_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_XEON_D_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_XEON_D_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- MSR_XEON_D_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
- MSR_XEON_D_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_ADDR 0x00000416\r
-#define MSR_XEON_D_MC6_ADDR 0x0000041A\r
-#define MSR_XEON_D_MC7_ADDR 0x0000041E\r
-#define MSR_XEON_D_MC8_ADDR 0x00000422\r
-#define MSR_XEON_D_MC9_ADDR 0x00000426\r
-#define MSR_XEON_D_MC10_ADDR 0x0000042A\r
-#define MSR_XEON_D_MC11_ADDR 0x0000042E\r
-#define MSR_XEON_D_MC12_ADDR 0x00000432\r
-#define MSR_XEON_D_MC13_ADDR 0x00000436\r
-#define MSR_XEON_D_MC14_ADDR 0x0000043A\r
-#define MSR_XEON_D_MC15_ADDR 0x0000043E\r
-#define MSR_XEON_D_MC16_ADDR 0x00000442\r
-#define MSR_XEON_D_MC17_ADDR 0x00000446\r
-#define MSR_XEON_D_MC18_ADDR 0x0000044A\r
-#define MSR_XEON_D_MC19_ADDR 0x0000044E\r
-#define MSR_XEON_D_MC20_ADDR 0x00000452\r
-#define MSR_XEON_D_MC21_ADDR 0x00000456\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_XEON_D_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);\r
- AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_XEON_D_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_XEON_D_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_XEON_D_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_XEON_D_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_XEON_D_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_XEON_D_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_XEON_D_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_XEON_D_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_XEON_D_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_XEON_D_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_XEON_D_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_XEON_D_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_XEON_D_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_XEON_D_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- MSR_XEON_D_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
- MSR_XEON_D_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_MISC 0x00000417\r
-#define MSR_XEON_D_MC6_MISC 0x0000041B\r
-#define MSR_XEON_D_MC7_MISC 0x0000041F\r
-#define MSR_XEON_D_MC8_MISC 0x00000423\r
-#define MSR_XEON_D_MC9_MISC 0x00000427\r
-#define MSR_XEON_D_MC10_MISC 0x0000042B\r
-#define MSR_XEON_D_MC11_MISC 0x0000042F\r
-#define MSR_XEON_D_MC12_MISC 0x00000433\r
-#define MSR_XEON_D_MC13_MISC 0x00000437\r
-#define MSR_XEON_D_MC14_MISC 0x0000043B\r
-#define MSR_XEON_D_MC15_MISC 0x0000043F\r
-#define MSR_XEON_D_MC16_MISC 0x00000443\r
-#define MSR_XEON_D_MC17_MISC 0x00000447\r
-#define MSR_XEON_D_MC18_MISC 0x0000044B\r
-#define MSR_XEON_D_MC19_MISC 0x0000044F\r
-#define MSR_XEON_D_MC20_MISC 0x00000453\r
-#define MSR_XEON_D_MC21_MISC 0x00000457\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_XEON_D_PKG_C8_RESIDENCY (0x00000630)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_D_PKG_C8_RESIDENCY 0x00000630\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PKG_C8_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r
- /// that this package is in processor-specific C8 states. Count at the\r
- /// same frequency as the TSC.\r
- ///\r
- UINT32 C8ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C8 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C8ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_XEON_D_PKG_C9_RESIDENCY (0x00000631)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_D_PKG_C9_RESIDENCY 0x00000631\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PKG_C9_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r
- /// that this package is in processor-specific C9 states. Count at the\r
- /// same frequency as the TSC.\r
- ///\r
- UINT32 C9ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C9 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C9ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_XEON_D_PKG_C10_RESIDENCY (0x00000632)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_D_PKG_C10_RESIDENCY 0x00000632\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PKG_C10_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C10 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C10ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C10 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C10ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER;\r
-\r
-\r
/**\r
Package. Cache Allocation Technology Configuration (R/W).\r
\r
projects / mirror_edk2.git / blobdiff