#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \\r
(DisplayFamily == 0x06 && \\r
( \\r
- DisplayModel == 0x57 \\r
+ DisplayModel == 0x57 || \\r
+ DisplayModel == 0x85 \\r
) \\r
)\r
\r
UINT64 Uint64;\r
} MSR_XEON_PHI_SMI_COUNT_REGISTER;\r
\r
+/**\r
+ Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r
\r
/**\r
- Package. See http://biosbits.org.\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to\r
+ /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if\r
+ /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an\r
+ /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a\r
+ /// privileged inventory initialization agent to access MSR_PPIN. After\r
+ /// reading MSR_PPIN, the privileged inventory initialization agent should\r
+ /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
+ /// prevent unauthorized modification to MSR_PPIN_CTL.\r
+ ///\r
+ UINT32 LockOut:1;\r
+ ///\r
+ /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
+ /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r
+ /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r
+ /// Default is 0.\r
+ ///\r
+ UINT32 Enable_PPIN:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+ Inventory Number (R/O) A unique value within a given CPUID\r
+ family/model/stepping signature that a privileged inventory initialization\r
+ agent can access to identify each physical processor, when access to\r
+ MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r
+ MSR_PPIN_CTL[bits 1:0] = '10b'.\r
+\r
+ @param ECX MSR_XEON_PHI_PPIN (0x0000004F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PPIN 0x0000004F\r
+\r
+/**\r
+ Package. Platform Information Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
\r
@param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r
@param EAX Lower 32-bits of MSR value.\r
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
\r
\r
+/**\r
+ Thread. MISC_FEATURE_ENABLES.\r
+\r
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r
+ /// MWAIT instructions do not cause invalid-opcode exceptions when\r
+ /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed\r
+ /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state\r
+ /// other than C0 or C1, the instruction operates as if EAX indicated the\r
+ /// C-state C1.\r
+ ///\r
+ UINT32 UserModeMonitorAndMwait:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r
+\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ UINT32 Reserved1:23;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_LBR_SELECT_REGISTER;\r
+\r
/**\r
Thread. Last Branch Record Stack TOS (R/W).\r
\r
\r
\r
/**\r
- Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
RAPL Domains.".\r
\r
@param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r
projects / mirror_edk2.git / blobdiff