UefiCpuPkg/BaseUefiCpuLib: Remove .S files for IA32 and X64 arch

[mirror_edk2.git] / UefiCpuPkg / Library / BaseUefiCpuLib / Ia32 / InitializeFpu.S

diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
deleted file mode 100644 (file)
index 0a1a919..0000000
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
+++ /dev/null
@@ -1,73 +0,0 @@
-#------------------------------------------------------------------------------\r
-#*\r
-#*   Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
-#*   This program and the accompanying materials\r
-#*   are licensed and made available under the terms and conditions of the BSD License\r
-#*   which accompanies this distribution.  The full text of the license may be found at\r
-#*   http://opensource.org/licenses/bsd-license.php\r
-#*\r
-#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#*\r
-#*\r
-#------------------------------------------------------------------------------\r
-\r
-#\r
-# Float control word initial value:\r
-# all exceptions masked, double-precision, round-to-nearest\r
-#\r
-ASM_PFX(mFpuControlWord): .word     0x027F\r
-#\r
-# Multimedia-extensions control word:\r
-# all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
-#\r
-ASM_PFX(mMmxControlWord): .long     0x01F80\r
-\r
-#\r
-# Initializes floating point units for requirement of UEFI specification.\r
-#\r
-# This function initializes floating-point control word to 0x027F (all exceptions\r
-# masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
-# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-# for masked underflow).\r
-#\r
-ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)\r
-ASM_PFX(InitializeFloatingPointUnits):\r
-\r
-    pushl   %ebx\r
-\r
-    #\r
-    # Initialize floating point units\r
-    #\r
-    finit\r
-    fldcw   ASM_PFX(mFpuControlWord)\r
-\r
-    #\r
-    # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
-    # whether the processor supports SSE instruction.\r
-    #\r
-    movl    $1,  %eax\r
-    cpuid\r
-    btl     $25, %edx\r
-    jnc     Done\r
-\r
-    #\r
-    # Set OSFXSR bit 9 in CR4\r
-    #\r
-    movl    %cr4, %eax\r
-    or      $0x200, %eax\r
-    movl    %eax, %cr4\r
-\r
-    #\r
-    # The processor should support SSE instruction and we can use\r
-    # ldmxcsr instruction\r
-    #\r
-    ldmxcsr ASM_PFX(mMmxControlWord)\r
-\r
-Done:\r
-    popl    %ebx\r
-\r
-    ret\r
-\r
-#END\r
-\r