Update the copyright notice format

[mirror_edk2.git] / UefiCpuPkg / Library / BaseUefiCpuLib / Ia32 / InitializeFpu.S

diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
index c4a2f6fb83bd2b18bcb72bfc32359a4d838a0270..4972bc2e7f3b0394f1bff68577fcf0be25d66acd 100644 (file)
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
@@ -1,19 +1,17 @@
-#------------------------------------------------------------------------------
-#*
-#*   Copyright 2009, Intel Corporation
-#*   All rights reserved. This program and the accompanying materials
-#*   are licensed and made available under the terms and conditions of the BSD License
-#*   which accompanies this distribution.  The full text of the license may be found at
-#*   http://opensource.org/licenses/bsd-license.php
-#*
-#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#*
-#*
-#------------------------------------------------------------------------------
-
-
-
+#------------------------------------------------------------------------------\r
+#*\r
+#*   Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
+#*   This program and the accompanying materials\r
+#*   are licensed and made available under the terms and conditions of the BSD License\r
+#*   which accompanies this distribution.  The full text of the license may be found at\r
+#*   http://opensource.org/licenses/bsd-license.php\r
+#*\r
+#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#*\r
+#*\r
+#------------------------------------------------------------------------------\r
+\r
 #\r
 # Float control word initial value: \r
 # all exceptions masked, double-precision, round-to-nearest\r
@@ -23,18 +21,21 @@ ASM_PFX(mFpuControlWord): .word     0x027F
 # Multimedia-extensions control word:\r
 # all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
 #\r
-ASM_PFX(mMmxControlWord): .long     0x01F80
-
-#
+ASM_PFX(mMmxControlWord): .long     0x01F80\r
+\r
+#\r
 # Initializes floating point units for requirement of UEFI specification.\r
 #\r
 # This function initializes floating-point control word to 0x027F (all exceptions\r
 # masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
 # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-# for masked underflow).
-#
-ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
-ASM_PFX(InitializeFloatingPointUnits):
+# for masked underflow).\r
+#\r
+ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)\r
+ASM_PFX(InitializeFloatingPointUnits):\r
+\r
+    pushl   %ebx\r
+\r
     #\r
     # Initialize floating point units\r
     #\r
@@ -49,22 +50,24 @@ ASM_PFX(InitializeFloatingPointUnits):
     cpuid\r
     btl     $25, %edx\r
     jnc     Done\r
-    
-    #
-    # Set OSFXSR bit 9 in CR4
-    #
-    movl    %cr4, %eax 
-    or      $200, %eax
-    movl    %eax, %cr4
-    
+    \r
+    #\r
+    # Set OSFXSR bit 9 in CR4\r
+    #\r
+    movl    %cr4, %eax \r
+    or      $0x200, %eax\r
+    movl    %eax, %cr4\r
+    \r
     #\r
     # The processor should support SSE instruction and we can use\r
     # ldmxcsr instruction\r
     #\r
-    ldmxcsr ASM_PFX(mMmxControlWord)
-
-Done:
-    ret
-
-#END
-
+    ldmxcsr ASM_PFX(mMmxControlWord)\r
+\r
+Done:\r
+    popl    %ebx\r
+\r
+    ret\r
+\r
+#END\r
+\r