UefiCpuPkg: Remove X86 ASM and S files

[mirror_edk2.git] / UefiCpuPkg / Library / BaseUefiCpuLib / Ia32 / InitializeFpu.asm

diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm
deleted file mode 100644 (file)
index 3c31da9..0000000
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm
+++ /dev/null
@@ -1,79 +0,0 @@
-;------------------------------------------------------------------------------\r
-;*\r
-;*   Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>\r
-;*   This program and the accompanying materials\r
-;*   are licensed and made available under the terms and conditions of the BSD License\r
-;*   which accompanies this distribution.  The full text of the license may be found at\r
-;*   http://opensource.org/licenses/bsd-license.php\r
-;*\r
-;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;*\r
-;*    \r
-;------------------------------------------------------------------------------\r
-\r
-\r
-    .686\r
-    .model  flat,C\r
-    .const\r
-;\r
-; Float control word initial value: \r
-; all exceptions masked, double-precision, round-to-nearest\r
-;\r
-mFpuControlWord       DW      027Fh\r
-;\r
-; Multimedia-extensions control word:\r
-; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
-;\r
-mMmxControlWord       DD      01F80h \r
-\r
-    .xmm\r
-    .code\r
-\r
-;\r
-; Initializes floating point units for requirement of UEFI specification.\r
-;\r
-; This function initializes floating-point control word to 0x027F (all exceptions\r
-; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
-; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-; for masked underflow).\r
-;\r
-InitializeFloatingPointUnits PROC PUBLIC\r
-\r
-    push    ebx\r
-\r
-    ;\r
-    ; Initialize floating point units\r
-    ;\r
-    finit\r
-    fldcw   mFpuControlWord\r
-    \r
-    ;\r
-    ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
-    ; whether the processor supports SSE instruction.\r
-    ;\r
-    mov     eax, 1\r
-    cpuid\r
-    bt      edx, 25\r
-    jnc     Done\r
-    \r
-    ;\r
-    ; Set OSFXSR bit 9 in CR4\r
-    ;\r
-    mov     eax, cr4\r
-    or      eax, BIT9\r
-    mov     cr4, eax\r
-    \r
-    ;\r
-    ; The processor should support SSE instruction and we can use\r
-    ; ldmxcsr instruction\r
-    ;\r
-    ldmxcsr mMmxControlWord\r
-Done:\r
-    pop     ebx\r
-\r
-    ret\r
-\r
-InitializeFloatingPointUnits ENDP\r
-\r
-END\r