\r
This local APIC library instance supports xAPIC mode only.\r
\r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
**/\r
\r
#include <Register/Cpuid.h>\r
+#include <Register/Msr.h>\r
#include <Register/LocalApic.h>\r
\r
#include <Library/BaseLib.h>\r
VOID\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
if (!LocalApicBaseAddressMsrSupported ()) {\r
//\r
return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
}\r
\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
\r
- return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
- (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
\r
/**\r
IN UINTN BaseAddress\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
\r
return;\r
}\r
\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
\r
- ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r
- ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+ ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);\r
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
\r
- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
}\r
\r
/**\r
{\r
DEBUG_CODE (\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
//\r
// Check to see if the CPU supports the APIC Base Address MSR \r
//\r
if (LocalApicBaseAddressMsrSupported ()) {\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
//\r
// Local APIC should have been enabled\r
//\r
- ASSERT (ApicBaseMsr.Bits.En != 0);\r
- ASSERT (ApicBaseMsr.Bits.Extd == 0);\r
+ ASSERT (ApicBaseMsr.Bits.EN != 0);\r
+ ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r
}\r
}\r
);\r