UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions

[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 1fca66ef1b293b76483aa818d5e757c094e5d01c..8d0fb021092992bac3904fdfc1e8d15e3436078a 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r
-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -15,6 +15,7 @@
 **/\r
 \r
 #include <Register/Cpuid.h>\r
+#include <Register/Msr.h>\r
 #include <Register/LocalApic.h>\r
 \r
 #include <Library/BaseLib.h>\r
@@ -67,7 +68,7 @@ GetLocalApicBaseAddress (
   VOID\r
   )\r
 {\r
-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r
 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r
@@ -77,10 +78,10 @@ GetLocalApicBaseAddress (
     return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
   }\r
 \r
-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
   \r
-  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
-           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+           (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
 }\r
 \r
 /**\r
@@ -97,7 +98,7 @@ SetLocalApicBaseAddress (
   IN UINTN                BaseAddress\r
   )\r
 {\r
-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r
 \r
   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
 \r
@@ -108,12 +109,12 @@ SetLocalApicBaseAddress (
     return;\r
   }\r
 \r
-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
 \r
-  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);\r
-  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+  ApicBaseMsr.Bits.ApicBase   = (UINT32) (BaseAddress >> 12);\r
+  ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
 \r
-  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
 }\r
 \r
 /**\r
@@ -246,18 +247,18 @@ GetApicMode (
 {\r
   DEBUG_CODE (\r
     {\r
-      MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+      MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r
 \r
       //\r
       // Check to see if the CPU supports the APIC Base Address MSR \r
       //\r
       if (LocalApicBaseAddressMsrSupported ()) {\r
-        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
         //\r
         // Local APIC should have been enabled\r
         //\r
-        ASSERT (ApicBaseMsr.Bits.En != 0);\r
-        ASSERT (ApicBaseMsr.Bits.Extd == 0);\r
+        ASSERT (ApicBaseMsr.Bits.EN != 0);\r
+        ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r
       }\r
     }\r
   );\r