This local APIC library instance supports x2APIC capable processors\r
which have xAPIC and x2APIC modes.\r
\r
- Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
**/\r
\r
+#include <Register/Cpuid.h>\r
#include <Register/LocalApic.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/LocalApicLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/TimerLib.h>\r
+#include <Library/PcdLib.h>\r
\r
//\r
// Library internal functions\r
//\r
\r
+/**\r
+ Determine if the CPU supports the Local APIC Base Address MSR.\r
+\r
+ @retval TRUE The CPU supports the Local APIC Base Address MSR.\r
+ @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r
+\r
+**/\r
+BOOLEAN\r
+LocalApicBaseAddressMsrSupported (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEax;\r
+ UINTN FamilyId;\r
+ \r
+ AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
+ FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
+ if (FamilyId == 0x04 || FamilyId == 0x05) {\r
+ //\r
+ // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r
+ // Local APIC Base Address MSR\r
+ //\r
+ return FALSE;\r
+ }\r
+ return TRUE;\r
+}\r
+\r
/**\r
Retrieve the base address of local APIC.\r
\r
VOID\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
- \r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // If CPU does not support Local APIC Base Address MSR, then retrieve\r
+ // Local APIC Base Address from PCD\r
+ //\r
+ return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
+ }\r
+\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
\r
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
IN UINTN BaseAddress\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
\r
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // Ignore set request of the CPU does not support APIC Base Address MSR\r
+ //\r
+ return;\r
+ }\r
+\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
\r
ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r
UINT64 MsrValue;\r
LOCAL_APIC_ICR_LOW IcrLowReg;\r
UINTN LocalApciBaseAddress;\r
+ UINT32 IcrHigh;\r
+ BOOLEAN InterruptState;\r
\r
+ //\r
+ // Legacy APIC or X2APIC?\r
+ //\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
ASSERT (ApicId <= 0xff);\r
\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+\r
//\r
- // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
+ // Get base address of this LAPIC\r
//\r
LocalApciBaseAddress = GetLocalApicBaseAddress();\r
+\r
+ //\r
+ // Save existing contents of ICR high 32 bits\r
+ //\r
+ IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);\r
+\r
+ //\r
+ // Wait for DeliveryStatus clear in case a previous IPI\r
+ // is still being sent\r
+ //\r
+ do {\r
+ IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
+ } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
+\r
+ //\r
+ // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
+ //\r
MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
+\r
+ //\r
+ // Wait for DeliveryStatus clear again\r
+ //\r
do {\r
IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
} while (IcrLowReg.Bits.DeliveryStatus != 0);\r
+\r
+ //\r
+ // And restore old contents of ICR high\r
+ //\r
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
+\r
+ SetInterruptState (InterruptState);\r
+\r
} else {\r
//\r
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r
VOID\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // If CPU does not support APIC Base Address MSR, then return XAPIC mode\r
+ //\r
+ return LOCAL_APIC_MODE_XAPIC;\r
+ }\r
\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
//\r
If the specified local APIC mode can't be set as current, then ASSERT.\r
\r
@param ApicMode APIC mode to be set.\r
+\r
+ @note This API must not be called from an interrupt handler or SMI handler.\r
+ It may result in unpredictable behavior.\r
**/\r
VOID\r
EFIAPI\r
IN UINTN ApicMode\r
)\r
{\r
- UINTN CurrentMode;\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ UINTN CurrentMode;\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // Ignore set request if the CPU does not support APIC Base Address MSR\r
+ //\r
+ return;\r
+ }\r
\r
CurrentMode = GetApicMode ();\r
if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {\r
ASSERT ((StartupRoutine & 0xfff) == 0);\r
\r
SendInitIpi (ApicId);\r
- MicroSecondDelay (10);\r
+ MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
IcrLow.Uint32 = 0;\r
IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
ASSERT ((StartupRoutine & 0xfff) == 0);\r
\r
SendInitIpiAllExcludingSelf ();\r
- MicroSecondDelay (10);\r
+ MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
IcrLow.Uint32 = 0;\r
IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
/**\r
Get the state of the local APIC timer.\r
\r
+ This function will ASSERT if the local APIC is not software enabled.\r
+\r
@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
@param Vector Return the timer interrupt vector number.\r
LOCAL_APIC_DCR Dcr;\r
LOCAL_APIC_LVT_TIMER LvtTimer;\r
\r
+ //\r
+ // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
+ // Vector Register.\r
+ // This bit will be 1, if local APIC is software enabled.\r
+ //\r
+ ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
+\r
if (DivideValue != NULL) {\r
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
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