+/**\r
+ Get the 32-bit address that a device should use to send a Message Signaled \r
+ Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+ @return 32-bit address used to send an MSI to the Local APIC.\r
+**/\r
+UINT32\r
+EFIAPI \r
+GetApicMsiAddress (\r
+ VOID\r
+ )\r
+{\r
+ LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
+\r
+ //\r
+ // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+ // of the currently executing processor.\r
+ //\r
+ MsiAddress.Uint32 = 0;\r
+ MsiAddress.Bits.BaseAddress = 0xFEE;\r
+ MsiAddress.Bits.DestinationId = GetApicId ();\r
+ return MsiAddress.Uint32;\r
+}\r
+ \r
+/**\r
+ Get the 64-bit data value that a device should use to send a Message Signaled \r
+ Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+ If Vector is not in range 0x10..0xFE, then ASSERT().\r
+ If DeliveryMode is not supported, then ASSERT().\r
+ \r
+ @param Vector The 8-bit interrupt vector associated with the MSI. \r
+ Must be in the range 0x10..0xFE\r
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
+ is handled. The only supported values are:\r
+ 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
+ 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
+ 2: LOCAL_APIC_DELIVERY_MODE_SMI\r
+ 4: LOCAL_APIC_DELIVERY_MODE_NMI\r
+ 5: LOCAL_APIC_DELIVERY_MODE_INIT\r
+ 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
+ \r
+ @param LevelTriggered TRUE specifies a level triggered interrupt. \r
+ FALSE specifies an edge triggered interrupt.\r
+ @param AssertionLevel Ignored if LevelTriggered is FALSE.\r
+ TRUE specifies a level triggered interrupt that active \r
+ when the interrupt line is asserted.\r
+ FALSE specifies a level triggered interrupt that active \r
+ when the interrupt line is deasserted.\r
+\r
+ @return 64-bit data value used to send an MSI to the Local APIC.\r
+**/\r
+UINT64\r
+EFIAPI \r
+GetApicMsiValue (\r
+ IN UINT8 Vector,\r
+ IN UINTN DeliveryMode,\r
+ IN BOOLEAN LevelTriggered,\r
+ IN BOOLEAN AssertionLevel\r
+ )\r
+{\r
+ LOCAL_APIC_MSI_DATA MsiData;\r
+\r
+ ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
+ ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
+ \r
+ MsiData.Uint64 = 0;\r
+ MsiData.Bits.Vector = Vector;\r
+ MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
+ if (LevelTriggered) {\r
+ MsiData.Bits.TriggerMode = 1;\r
+ if (AssertionLevel) {\r
+ MsiData.Bits.Level = 1;\r
+ }\r
+ }\r
+ return MsiData.Uint64;\r
+}\r
+\r
+/**\r
+ Get Package ID/Core ID/Thread ID of a processor.\r
+\r
+ The algorithm assumes the target system has symmetry across physical\r
+ package boundaries with respect to the number of logical processors\r
+ per package, number of cores per package.\r
+\r
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
+ @param[out] Package Returns the processor package ID.\r
+ @param[out] Core Returns the processor core ID.\r
+ @param[out] Thread Returns the processor thread ID.\r
+**/\r
+VOID\r
+EFIAPI\r
+GetProcessorLocationByApicId (\r
+ IN UINT32 InitialApicId,\r
+ OUT UINT32 *Package OPTIONAL,\r
+ OUT UINT32 *Core OPTIONAL,\r
+ OUT UINT32 *Thread OPTIONAL\r
+ )\r
+{\r
+ BOOLEAN TopologyLeafSupported;\r
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r
+ UINT32 MaxStandardCpuIdIndex;\r
+ UINT32 MaxExtendedCpuIdIndex;\r
+ UINT32 SubIndex;\r
+ UINTN LevelType;\r
+ UINT32 MaxLogicProcessorsPerPackage;\r
+ UINT32 MaxCoresPerPackage;\r
+ UINTN ThreadBits;\r
+ UINTN CoreBits;\r
+\r
+ //\r
+ // Check if the processor is capable of supporting more than one logical processor.\r
+ //\r
+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+ if (VersionInfoEdx.Bits.HTT == 0) {\r
+ if (Thread != NULL) {\r
+ *Thread = 0;\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = 0;\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = 0;\r
+ }\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Assume three-level mapping of APIC ID: Package|Core|Thread.\r
+ //\r
+ ThreadBits = 0;\r
+ CoreBits = 0;\r
+\r
+ //\r
+ // Get max index of CPUID\r
+ //\r
+ AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
+\r
+ //\r
+ // If the extended topology enumeration leaf is available, it\r
+ // is the preferred mechanism for enumerating topology.\r
+ //\r
+ TopologyLeafSupported = FALSE;\r
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
+ AsmCpuidEx(\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ 0,\r
+ &ExtendedTopologyEax.Uint32,\r
+ &ExtendedTopologyEbx.Uint32,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ //\r
+ // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
+ // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
+ // supported on that processor.\r
+ //\r
+ if (ExtendedTopologyEbx.Uint32 != 0) {\r
+ TopologyLeafSupported = TRUE;\r
+\r
+ //\r
+ // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
+ // the SMT sub-field of x2APIC ID.\r
+ //\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
+ ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
+\r
+ //\r
+ // Software must not assume any "level type" encoding\r
+ // value to be related to any sub-leaf index, except sub-leaf 0.\r
+ //\r
+ SubIndex = 1;\r
+ do {\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ SubIndex,\r
+ &ExtendedTopologyEax.Uint32,\r
+ NULL,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
+ CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
+ break;\r
+ }\r
+ SubIndex++;\r
+ } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
+ }\r
+ }\r
+\r
+ if (!TopologyLeafSupported) {\r
+ //\r
+ // Get logical processor count\r
+ //\r
+ AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
+\r
+ //\r
+ // Assume single-core processor\r
+ //\r
+ MaxCoresPerPackage = 1;\r
+\r
+ //\r
+ // Check for topology extensions on AMD processor\r
+ //\r
+ if (StandardSignatureIsAuthenticAMD()) {\r
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
+ //\r
+ // Account for max possible thread count to decode ApicId\r
+ //\r
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
+ MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
+\r
+ //\r
+ // Get cores per processor package\r
+ //\r
+ AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
+ }\r
+ }\r
+ }\r
+ else {\r
+ //\r
+ // Extract core count based on CACHE information\r
+ //\r
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
+ AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+ if (CacheParamsEax.Uint32 != 0) {\r
+ MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r
+ }\r
+\r
+ if (Thread != NULL) {\r
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
+ }\r
+}\r