This local APIC library instance supports x2APIC capable processors\r
which have xAPIC and x2APIC modes.\r
\r
- Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Library internal functions\r
//\r
\r
+/**\r
+ Determine if the CPU supports the Local APIC Base Address MSR.\r
+\r
+ @retval TRUE The CPU supports the Local APIC Base Address MSR.\r
+ @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r
+\r
+**/\r
+BOOLEAN\r
+LocalApicBaseAddressMsrSupported (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEax;\r
+ UINTN FamilyId;\r
+ \r
+ AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
+ FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
+ if (FamilyId == 0x04 || FamilyId == 0x05) {\r
+ //\r
+ // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r
+ // Local APIC Base Address MSR\r
+ //\r
+ return FALSE;\r
+ }\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Retrieve the base address of local APIC.\r
+\r
+ @return The base address of local APIC.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+GetLocalApicBaseAddress (\r
+ VOID\r
+ )\r
+{\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // If CPU does not support Local APIC Base Address MSR, then retrieve\r
+ // Local APIC Base Address from PCD\r
+ //\r
+ return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
+ }\r
+\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ \r
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
+ (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+}\r
+\r
+/**\r
+ Set the base address of local APIC.\r
+\r
+ If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
+\r
+ @param[in] BaseAddress Local APIC base address to be set.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetLocalApicBaseAddress (\r
+ IN UINTN BaseAddress\r
+ )\r
+{\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
+\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // Ignore set request of the CPU does not support APIC Base Address MSR\r
+ //\r
+ return;\r
+ }\r
+\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+\r
+ ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r
+ ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+\r
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+}\r
+\r
/**\r
Read from a local APIC register.\r
\r
ASSERT ((MmioOffset & 0xf) == 0);\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
- return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);\r
+ return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
} else {\r
//\r
// DFR is not supported in x2APIC mode.\r
ASSERT ((MmioOffset & 0xf) == 0);\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);\r
+ MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
} else {\r
//\r
// DFR is not supported in x2APIC mode.\r
{\r
UINT64 MsrValue;\r
LOCAL_APIC_ICR_LOW IcrLowReg;\r
+ UINTN LocalApciBaseAddress;\r
+ UINT32 IcrHigh;\r
+ BOOLEAN InterruptState;\r
\r
+ //\r
+ // Legacy APIC or X2APIC?\r
+ //\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
ASSERT (ApicId <= 0xff);\r
\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+\r
+ //\r
+ // Get base address of this LAPIC\r
+ //\r
+ LocalApciBaseAddress = GetLocalApicBaseAddress();\r
+\r
+ //\r
+ // Save existing contents of ICR high 32 bits\r
+ //\r
+ IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);\r
+\r
+ //\r
+ // Wait for DeliveryStatus clear in case a previous IPI\r
+ // is still being sent\r
+ //\r
+ do {\r
+ IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
+ } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
+\r
//\r
// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
//\r
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
+\r
+ //\r
+ // Wait for DeliveryStatus clear again\r
+ //\r
do {\r
- IcrLowReg.Uint32 = MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET);\r
+ IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
} while (IcrLowReg.Bits.DeliveryStatus != 0);\r
+\r
+ //\r
+ // And restore old contents of ICR high\r
+ //\r
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
+\r
+ SetInterruptState (InterruptState);\r
+\r
} else {\r
//\r
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r
VOID\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // If CPU does not support APIC Base Address MSR, then return XAPIC mode\r
+ //\r
+ return LOCAL_APIC_MODE_XAPIC;\r
+ }\r
\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
//\r
If the specified local APIC mode can't be set as current, then ASSERT.\r
\r
@param ApicMode APIC mode to be set.\r
+\r
+ @note This API must not be called from an interrupt handler or SMI handler.\r
+ It may result in unpredictable behavior.\r
**/\r
VOID\r
EFIAPI\r
IN UINTN ApicMode\r
)\r
{\r
- UINTN CurrentMode;\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ UINTN CurrentMode;\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ if (!LocalApicBaseAddressMsrSupported ()) {\r
+ //\r
+ // Ignore set request if the CPU does not support APIC Base Address MSR\r
+ //\r
+ return;\r
+ }\r
\r
CurrentMode = GetApicMode ();\r
if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {\r
/**\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
- In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.\r
+ In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
VOID\r
)\r
{\r
+ UINT32 ApicId;\r
+ UINT32 MaxCpuIdIndex;\r
UINT32 RegEbx;\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
+ //\r
+ // Get the max index of basic CPUID\r
+ //\r
+ AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
+ //\r
+ // If CPUID Leaf B is supported, \r
+ // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
+ // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
+ //\r
+ if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
+ AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);\r
+ return ApicId;\r
+ }\r
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
return RegEbx >> 24;\r
} else {\r
)\r
{\r
UINT32 ApicId;\r
+ UINT32 InitApicId;\r
\r
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
- ApicId >>= 24;\r
+ ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;\r
}\r
+\r
return ApicId;\r
}\r
\r
ASSERT ((StartupRoutine & 0xfff) == 0);\r
\r
SendInitIpi (ApicId);\r
- MicroSecondDelay (10);\r
+ MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
IcrLow.Uint32 = 0;\r
IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
ASSERT ((StartupRoutine & 0xfff) == 0);\r
\r
SendInitIpiAllExcludingSelf ();\r
- MicroSecondDelay (10);\r
+ MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
IcrLow.Uint32 = 0;\r
IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
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