X2Apic feature.\r
\r
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "CpuCommonFeatures.h"\r
\r
+/**\r
+ Prepares for the data used by CPU feature detection and initialization.\r
+\r
+ @param[in] NumberOfProcessors The number of CPUs in the platform.\r
+\r
+ @return Pointer to a buffer of CPU related configuration data.\r
+\r
+ @note This service could be called by BSP only.\r
+**/\r
+VOID *\r
+EFIAPI\r
+X2ApicGetConfigData (\r
+ IN UINTN NumberOfProcessors\r
+ )\r
+{\r
+ BOOLEAN *ConfigData;\r
+\r
+ ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);\r
+ ASSERT (ConfigData != NULL);\r
+ return ConfigData;\r
+}\r
+\r
/**\r
Detects if X2Apci feature supported on current processor.\r
\r
IN VOID *ConfigData OPTIONAL\r
)\r
{\r
- return (GetApicMode () == LOCAL_APIC_MODE_X2APIC);\r
+ BOOLEAN *X2ApicEnabled;\r
+\r
+ ASSERT (ConfigData != NULL);\r
+ X2ApicEnabled = (BOOLEAN *) ConfigData;\r
+ //\r
+ // *ConfigData indicates if X2APIC enabled on current processor\r
+ //\r
+ X2ApicEnabled[ProcessorNumber] = (GetApicMode () == LOCAL_APIC_MODE_X2APIC) ? TRUE : FALSE;\r
+\r
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.x2APIC == 1);\r
}\r
\r
/**\r
IN BOOLEAN State\r
)\r
{\r
- PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (\r
- ProcessorNumber,\r
- Msr,\r
- MSR_IA32_APIC_BASE,\r
- MSR_IA32_APIC_BASE_REGISTER,\r
- Bits.EXTD,\r
- (State) ? 1 : 0\r
- );\r
+ BOOLEAN *X2ApicEnabled;\r
+\r
+ //\r
+ // The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program\r
+ // MSR_IA32_APIC_BASE for thread 0 in each core.\r
+ //\r
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+ }\r
+\r
+ ASSERT (ConfigData != NULL);\r
+ X2ApicEnabled = (BOOLEAN *) ConfigData;\r
+ if (X2ApicEnabled[ProcessorNumber]) {\r
+ PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (\r
+ ProcessorNumber,\r
+ Msr,\r
+ MSR_IA32_APIC_BASE,\r
+ MSR_IA32_APIC_BASE_REGISTER,\r
+ Bits.EXTD,\r
+ 1\r
+ );\r
+ } else {\r
+ //\r
+ // Enable X2APIC mode only if X2APIC is not enabled,\r
+ // Needn't to disabe X2APIC mode again if X2APIC is not enabled\r
+ //\r
+ if (State) {\r
+ CPU_REGISTER_TABLE_WRITE_FIELD (\r
+ ProcessorNumber,\r
+ Msr,\r
+ MSR_IA32_APIC_BASE,\r
+ MSR_IA32_APIC_BASE_REGISTER,\r
+ Bits.EXTD,\r
+ 1\r
+ );\r
+ }\r
+ }\r
return RETURN_SUCCESS;\r
}\r