\r
#include <PiPei.h>\r
\r
-#include <Register/Cpuid.h>\r
-#include <Register/Msr.h>\r
-#include <Register/LocalApic.h>\r
-#include <Register/Microcode.h>\r
+#include <Register/Intel/Cpuid.h>\r
+#include <Register/Intel/Msr.h>\r
+#include <Register/Intel/LocalApic.h>\r
+#include <Register/Intel/Microcode.h>\r
\r
#include <Library/MpInitLib.h>\r
#include <Library/BaseLib.h>\r
#define CPU_SWITCH_STATE_STORED 1\r
#define CPU_SWITCH_STATE_LOADED 2\r
\r
+//\r
+// Default maximum number of entries to store the microcode patches information\r
+//\r
+#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8\r
+\r
+//\r
+// Data structure for microcode patch information\r
+//\r
+typedef struct {\r
+ UINTN Address;\r
+ UINTN Size;\r
+ UINTN AlignedSize;\r
+} MICROCODE_PATCH_INFO;\r
+\r
//\r
// CPU exchange information for switch BSP\r
//\r
UINT64 CurrentTime;\r
UINT64 TotalTime;\r
EFI_EVENT WaitEvent;\r
+ UINT32 ProcessorSignature;\r
+ UINT8 PlatformId;\r
+ UINT64 MicrocodeEntryAddr;\r
} CPU_AP_DATA;\r
\r
//\r
UINT16 ModeTransitionSegment;\r
UINT32 ModeHighMemory;\r
UINT16 ModeHighSegment;\r
+ //\r
+ // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.\r
+ //\r
+ BOOLEAN Enable5LevelPaging;\r
} MP_CPU_EXCHANGE_INFO;\r
\r
#pragma pack()\r
UINT64 CpuInfoInHob;\r
UINT32 CpuCount;\r
UINT32 BspNumber;\r
+ UINT64 MicrocodePatchAddress;\r
+ UINT64 MicrocodePatchRegionSize;\r
//\r
// The above fields data will be passed from PEI to DXE\r
// Please make sure the fields offset same in the different\r
UINTN **FailedCpuList;\r
\r
AP_INIT_STATE InitFlag;\r
- BOOLEAN X2ApicEnable;\r
BOOLEAN SwitchBspFlag;\r
UINTN NewBspNumber;\r
CPU_EXCHANGE_ROLE_INFO BSPInfo;\r
UINT8 Vector;\r
BOOLEAN PeriodicMode;\r
BOOLEAN TimerInterruptState;\r
- UINT64 MicrocodePatchAddress;\r
- UINT64 MicrocodePatchRegionSize;\r
-\r
- UINT32 ProcessorSignature;\r
- UINT32 ProcessorFlags;\r
- UINT64 MicrocodeDataAddress;\r
- UINT32 MicrocodeRevision;\r
\r
//\r
// Whether need to use Init-Sipi-Sipi to wake up the APs.\r
/**\r
Detect whether specified processor can find matching microcode patch and load it.\r
\r
- @param[in] CpuMpData The pointer to CPU MP Data structure.\r
- @param[in] IsBspCallIn Indicate whether the caller is BSP or not.\r
+ @param[in] CpuMpData The pointer to CPU MP Data structure.\r
+ @param[in] ProcessorNumber The handle number of the processor. The range is\r
+ from 0 to the total number of logical processors\r
+ minus 1.\r
**/\r
VOID\r
MicrocodeDetect (\r
IN CPU_MP_DATA *CpuMpData,\r
- IN BOOLEAN IsBspCallIn\r
+ IN UINTN ProcessorNumber\r
+ );\r
+\r
+/**\r
+ Load the required microcode patches data into memory.\r
+\r
+ @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
+**/\r
+VOID\r
+LoadMicrocodePatch (\r
+ IN OUT CPU_MP_DATA *CpuMpData\r
);\r
\r
/**\r
VOID\r
);\r
\r
+/**\r
+ Find the current Processor number by APIC ID.\r
+\r
+ @param[in] CpuMpData Pointer to PEI CPU MP Data\r
+ @param[out] ProcessorNumber Return the pocessor number found\r
+\r
+ @retval EFI_SUCCESS ProcessorNumber is found and returned.\r
+ @retval EFI_NOT_FOUND ProcessorNumber is not found.\r
+**/\r
+EFI_STATUS\r
+GetProcessorNumber (\r
+ IN CPU_MP_DATA *CpuMpData,\r
+ OUT UINTN *ProcessorNumber\r
+ );\r
+\r
#endif\r
\r