UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / UefiCpuPkg / Library / MpInitLib / MpLib.h

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index 59ab96089759e80e9867eefb2f446c22e0a4acdf..6f235dcf6d696b6a541948c1614f66c041005c2f 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -1,7 +1,7 @@
 /** @file\r
   Common header file for MP Initialize Library.\r
 \r
-  Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.<BR>\r
   Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
@@ -68,14 +68,31 @@ typedef struct {
   UINTN    Size;\r
 } MICROCODE_PATCH_INFO;\r
 \r
+//\r
+// CPU volatile registers around INIT-SIPI-SIPI\r
+//\r
+typedef struct {\r
+  UINTN              Cr0;\r
+  UINTN              Cr3;\r
+  UINTN              Cr4;\r
+  UINTN              Dr0;\r
+  UINTN              Dr1;\r
+  UINTN              Dr2;\r
+  UINTN              Dr3;\r
+  UINTN              Dr6;\r
+  UINTN              Dr7;\r
+  IA32_DESCRIPTOR    Gdtr;\r
+  IA32_DESCRIPTOR    Idtr;\r
+  UINT16             Tr;\r
+} CPU_VOLATILE_REGISTERS;\r
+\r
 //\r
 // CPU exchange information for switch BSP\r
 //\r
 typedef struct {\r
-  UINT8              State;        // offset 0\r
-  UINTN              StackPointer; // offset 4 / 8\r
-  IA32_DESCRIPTOR    Gdtr;         // offset 8 / 16\r
-  IA32_DESCRIPTOR    Idtr;         // offset 14 / 26\r
+  UINT8                     State;             // offset 0\r
+  UINTN                     StackPointer;      // offset 4 / 8\r
+  CPU_VOLATILE_REGISTERS    VolatileRegisters; // offset 8 / 16\r
 } CPU_EXCHANGE_ROLE_INFO;\r
 \r
 //\r
@@ -112,24 +129,6 @@ typedef enum {
   CpuStateDisabled\r
 } CPU_STATE;\r
 \r
-//\r
-// CPU volatile registers around INIT-SIPI-SIPI\r
-//\r
-typedef struct {\r
-  UINTN              Cr0;\r
-  UINTN              Cr3;\r
-  UINTN              Cr4;\r
-  UINTN              Dr0;\r
-  UINTN              Dr1;\r
-  UINTN              Dr2;\r
-  UINTN              Dr3;\r
-  UINTN              Dr6;\r
-  UINTN              Dr7;\r
-  IA32_DESCRIPTOR    Gdtr;\r
-  IA32_DESCRIPTOR    Idtr;\r
-  UINT16             Tr;\r
-} CPU_VOLATILE_REGISTERS;\r
-\r
 //\r
 // AP related data\r
 //\r
@@ -178,11 +177,11 @@ typedef struct {
   UINT8    *RendezvousFunnelAddress;\r
   UINTN    ModeEntryOffset;\r
   UINTN    RendezvousFunnelSize;\r
-  UINT8    *RelocateApLoopFuncAddress;\r
-  UINTN    RelocateApLoopFuncSize;\r
+  UINT8    *RelocateApLoopFuncAddressGeneric;\r
+  UINTN    RelocateApLoopFuncSizeGeneric;\r
+  UINT8    *RelocateApLoopFuncAddressAmdSev;\r
+  UINTN    RelocateApLoopFuncSizeAmdSev;\r
   UINTN    ModeTransitionOffset;\r
-  UINTN    SwitchToRealSize;\r
-  UINTN    SwitchToRealOffset;\r
   UINTN    SwitchToRealNoNxOffset;\r
   UINTN    SwitchToRealPM16ModeOffset;\r
   UINTN    SwitchToRealPM16ModeSize;\r
@@ -304,8 +303,17 @@ struct _CPU_MP_DATA {
   UINT64         GhcbBase;\r
 };\r
 \r
+//\r
+// AP_STACK_DATA is stored at the top of each AP stack.\r
+//\r
+typedef struct {\r
+  UINTN          Bist;\r
+  CPU_MP_DATA    *MpData;\r
+} AP_STACK_DATA;\r
+\r
 #define AP_SAFE_STACK_SIZE   128\r
 #define AP_RESET_STACK_SIZE  AP_SAFE_STACK_SIZE\r
+STATIC_ASSERT ((AP_SAFE_STACK_SIZE & (CPU_STACK_ALIGNMENT - 1)) == 0, "AP_SAFE_STACK_SIZE is not aligned with CPU_STACK_ALIGNMENT");\r
 \r
 #pragma pack(1)\r
 \r
@@ -357,7 +365,30 @@ extern EFI_GUID  mCpuInitMpLibHobGuid;
 **/\r
 typedef\r
   VOID\r
-(EFIAPI *ASM_RELOCATE_AP_LOOP)(\r
+(EFIAPI *ASM_RELOCATE_AP_LOOP_GENERIC)(\r
+  IN BOOLEAN                 MwaitSupport,\r
+  IN UINTN                   ApTargetCState,\r
+  IN UINTN                   TopOfApStack,\r
+  IN UINTN                   NumberToFinish,\r
+  IN UINTN                   Cr3\r
+  );\r
+\r
+/**\r
+  Assembly code to place AP into safe loop mode for Amd processors\r
+  with Sev enabled.\r
+  Place AP into targeted C-State if MONITOR is supported, otherwise\r
+  place AP into hlt state.\r
+  Place AP in protected mode if the current is long mode. Due to AP maybe\r
+  wakeup by some hardware event. It could avoid accessing page table that\r
+  may not available during booting to OS.\r
+  @param[in] MwaitSupport    TRUE indicates MONITOR is supported.\r
+                             FALSE indicates MONITOR is not supported.\r
+  @param[in] ApTargetCState  Target C-State value.\r
+  @param[in] PmCodeSegment   Protected mode code segment value.\r
+**/\r
+typedef\r
+  VOID\r
+(EFIAPI *ASM_RELOCATE_AP_LOOP_AMDSEV)(\r
   IN BOOLEAN                 MwaitSupport,\r
   IN UINTN                   ApTargetCState,\r
   IN UINTN                   PmCodeSegment,\r
@@ -396,6 +427,12 @@ AsmExchangeRole (
   IN CPU_EXCHANGE_ROLE_INFO  *OthersInfo\r
   );\r
 \r
+typedef union {\r
+  VOID                            *Data;\r
+  ASM_RELOCATE_AP_LOOP_AMDSEV     AmdSevEntry;  // 64-bit AMD Sev processors\r
+  ASM_RELOCATE_AP_LOOP_GENERIC    GenericEntry; // Intel processors (32-bit or 64-bit), 32-bit AMD processors, or AMD non-Sev processors\r
+} RELOCATE_AP_LOOP_ENTRY;\r
+\r
 /**\r
   Get the pointer to CPU MP Data structure.\r
 \r
@@ -459,6 +496,18 @@ GetSevEsAPMemory (
   VOID\r
   );\r
 \r
+/**\r
+  Create 1:1 mapping page table in reserved memory to map the specified address range.\r
+  @param[in]      LinearAddress  The start of the linear address range.\r
+  @param[in]      Length         The length of the linear address range.\r
+  @return The page table to be created.\r
+**/\r
+UINTN\r
+CreatePageTable (\r
+  IN UINTN  Address,\r
+  IN UINTN  Length\r
+  );\r
+\r
 /**\r
   This function will be called by BSP to wakeup AP.\r
 \r