CpuStateDisabled\r
} CPU_STATE;\r
\r
+//\r
+// CPU volatile registers around INIT-SIPI-SIPI\r
+//\r
+typedef struct {\r
+ UINTN Cr0;\r
+ UINTN Cr3;\r
+ UINTN Cr4;\r
+ UINTN Dr0;\r
+ UINTN Dr1;\r
+ UINTN Dr2;\r
+ UINTN Dr3;\r
+ UINTN Dr6;\r
+ UINTN Dr7;\r
+} CPU_VOLATILE_REGISTERS;\r
+\r
//\r
// AP related data\r
//\r
UINT32 Health;\r
BOOLEAN CpuHealthy;\r
volatile CPU_STATE State;\r
+ CPU_VOLATILE_REGISTERS VolatileRegisters;\r
BOOLEAN Waiting;\r
BOOLEAN *Finished;\r
UINT64 ExpectedTime;\r