+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SmiEntry.asm\r
-;\r
-; Abstract:\r
-;\r
-; Code template of the SMI handler for a particular processor\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
- .686p\r
- .model flat,C\r
- .xmm\r
-\r
-MSR_IA32_MISC_ENABLE EQU 1A0h\r
-MSR_EFER EQU 0c0000080h\r
-MSR_EFER_XD EQU 0800h\r
-\r
-;\r
-; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR\r
-;\r
-DSC_OFFSET EQU 0fb00h\r
-DSC_GDTPTR EQU 48h\r
-DSC_GDTSIZ EQU 50h\r
-DSC_CS EQU 14h\r
-DSC_DS EQU 16h\r
-DSC_SS EQU 18h\r
-DSC_OTHERSEG EQU 1Ah\r
-\r
-PROTECT_MODE_CS EQU 08h\r
-PROTECT_MODE_DS EQU 20h\r
-TSS_SEGMENT EQU 40h\r
-\r
-SmiRendezvous PROTO C\r
-CpuSmmDebugEntry PROTO C\r
-CpuSmmDebugExit PROTO C\r
-\r
-EXTERNDEF gcStmSmiHandlerTemplate:BYTE\r
-EXTERNDEF gcStmSmiHandlerSize:WORD\r
-EXTERNDEF gcStmSmiHandlerOffset:WORD\r
-EXTERNDEF gStmSmiCr3:DWORD\r
-EXTERNDEF gStmSmiStack:DWORD\r
-EXTERNDEF gStmSmbase:DWORD\r
-EXTERNDEF gStmXdSupported:BYTE\r
-EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE\r
-EXTERNDEF gStmSmiHandlerIdtr:FWORD\r
-\r
- .code\r
-\r
-gcStmSmiHandlerTemplate LABEL BYTE\r
-\r
-_StmSmiEntryPoint:\r
- DB 0bbh ; mov bx, imm16\r
- DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h\r
- DB 2eh, 0a1h ; mov ax, cs:[offset16]\r
- DW DSC_OFFSET + DSC_GDTSIZ\r
- dec eax\r
- mov cs:[edi], eax ; mov cs:[bx], ax\r
- DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]\r
- DW DSC_OFFSET + DSC_GDTPTR\r
- mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax\r
- mov bp, ax ; ebp = GDT base\r
- DB 66h\r
- lgdt fword ptr cs:[edi] ; lgdt fword ptr cs:[bx]\r
-; Patch ProtectedMode Segment\r
- DB 0b8h ; mov ax, imm16\r
- DW PROTECT_MODE_CS ; set AX for segment directly\r
- mov cs:[edi - 2], eax ; mov cs:[bx - 2], ax\r
-; Patch ProtectedMode entry\r
- DB 66h, 0bfh ; mov edi, SMBASE\r
-gStmSmbase DD ?\r
- DB 67h\r
- lea ax, [edi + (@32bit - _StmSmiEntryPoint) + 8000h]\r
- mov cs:[edi - 6], ax ; mov cs:[bx - 6], eax\r
- mov ebx, cr0\r
- DB 66h\r
- and ebx, 9ffafff3h\r
- DB 66h\r
- or ebx, 23h\r
- mov cr0, ebx\r
- DB 66h, 0eah\r
- DD ?\r
- DW ?\r
-_StmGdtDesc FWORD ?\r
-\r
-@32bit:\r
- mov ax, PROTECT_MODE_DS\r
- mov ds, ax\r
- mov es, ax\r
- mov fs, ax\r
- mov gs, ax\r
- mov ss, ax\r
- DB 0bch ; mov esp, imm32\r
-gStmSmiStack DD ?\r
- mov eax, offset gStmSmiHandlerIdtr\r
- lidt fword ptr [eax]\r
- jmp ProtFlatMode\r
-\r
-ProtFlatMode:\r
- DB 0b8h ; mov eax, imm32\r
-gStmSmiCr3 DD ?\r
- mov cr3, eax\r
-;\r
-; Need to test for CR4 specific bit support\r
-;\r
- mov eax, 1\r
- cpuid ; use CPUID to determine if specific CR4 bits are supported\r
- xor eax, eax ; Clear EAX\r
- test edx, BIT2 ; Check for DE capabilities\r
- jz @f\r
- or eax, BIT3\r
-@@:\r
- test edx, BIT6 ; Check for PAE capabilities\r
- jz @f\r
- or eax, BIT5\r
-@@:\r
- test edx, BIT7 ; Check for MCE capabilities\r
- jz @f\r
- or eax, BIT6\r
-@@:\r
- test edx, BIT24 ; Check for FXSR capabilities\r
- jz @f\r
- or eax, BIT9\r
-@@:\r
- test edx, BIT25 ; Check for SSE capabilities\r
- jz @f\r
- or eax, BIT10\r
-@@: ; as cr4.PGE is not set here, refresh cr3\r
- mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
-\r
- cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0\r
- jz @F\r
-; Load TSS\r
- mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r
- mov eax, TSS_SEGMENT\r
- ltr ax\r
-@@:\r
-\r
-; enable NXE if supported\r
- DB 0b0h ; mov al, imm8\r
-gStmXdSupported DB 1\r
- cmp al, 0\r
- jz @SkipXd\r
-;\r
-; Check XD disable bit\r
-;\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
- jmp @XdDone\r
-@SkipXd:\r
- sub esp, 4\r
-@XdDone:\r
-\r
- mov ebx, cr0\r
- or ebx, 080010023h ; enable paging + WP + NE + MP + PE\r
- mov cr0, ebx\r
- lea ebx, [edi + DSC_OFFSET]\r
- mov ax, [ebx + DSC_DS]\r
- mov ds, eax\r
- mov ax, [ebx + DSC_OTHERSEG]\r
- mov es, eax\r
- mov fs, eax\r
- mov gs, eax\r
- mov ax, [ebx + DSC_SS]\r
- mov ss, eax\r
-\r
-CommonHandler:\r
- mov ebx, [esp + 4] ; CPU Index\r
- push ebx\r
- mov eax, CpuSmmDebugEntry\r
- call eax\r
- add esp, 4\r
-\r
- push ebx\r
- mov eax, SmiRendezvous\r
- call eax\r
- add esp, 4\r
-\r
- push ebx\r
- mov eax, CpuSmmDebugExit\r
- call eax\r
- add esp, 4\r
-\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @f\r
- pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2\r
- jz @f\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
- wrmsr\r
-\r
-@@:\r
- rsm\r
-\r
-_StmSmiHandler:\r
-;\r
-; Check XD disable bit\r
-;\r
- xor esi, esi\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @StmXdDone\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
-@StmXdDone:\r
- push esi\r
-\r
- ; below step is needed, because STM does not run above code.\r
- ; we have to run below code to set IDT/CR0/CR4\r
- mov eax, offset gStmSmiHandlerIdtr\r
- lidt fword ptr [eax]\r
-\r
-\r
- mov eax, cr0\r
- or eax, 80010023h ; enable paging + WP + NE + MP + PE\r
- mov cr0, eax\r
-;\r
-; Need to test for CR4 specific bit support\r
-;\r
- mov eax, 1\r
- cpuid ; use CPUID to determine if specific CR4 bits are supported\r
- mov eax, cr4 ; init EAX\r
- test edx, BIT2 ; Check for DE capabilities\r
- jz @f\r
- or eax, BIT3\r
-@@:\r
- test edx, BIT6 ; Check for PAE capabilities\r
- jz @f\r
- or eax, BIT5\r
-@@:\r
- test edx, BIT7 ; Check for MCE capabilities\r
- jz @f\r
- or eax, BIT6\r
-@@:\r
- test edx, BIT24 ; Check for FXSR capabilities\r
- jz @f\r
- or eax, BIT9\r
-@@:\r
- test edx, BIT25 ; Check for SSE capabilities\r
- jz @f\r
- or eax, BIT10\r
-@@: ; as cr4.PGE is not set here, refresh cr3\r
- mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
- ; STM init finish\r
- jmp CommonHandler\r
-\r
-gcStmSmiHandlerSize DW $ - _StmSmiEntryPoint\r
-gcStmSmiHandlerOffset DW _StmSmiHandler - _StmSmiEntryPoint\r
-\r
- END\r
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