--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; SmiEntry.nasm\r
+;\r
+; Abstract:\r
+;\r
+; Code template of the SMI handler for a particular processor\r
+;\r
+;-------------------------------------------------------------------------------\r
+\r
+%define MSR_IA32_MISC_ENABLE 0x1A0\r
+%define MSR_EFER 0xc0000080\r
+%define MSR_EFER_XD 0x800\r
+\r
+;\r
+; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR\r
+;\r
+%define DSC_OFFSET 0xfb00\r
+%define DSC_GDTPTR 0x48\r
+%define DSC_GDTSIZ 0x50\r
+%define DSC_CS 0x14\r
+%define DSC_DS 0x16\r
+%define DSC_SS 0x18\r
+%define DSC_OTHERSEG 0x1a\r
+\r
+%define PROTECT_MODE_CS 0x8\r
+%define PROTECT_MODE_DS 0x20\r
+%define TSS_SEGMENT 0x40\r
+\r
+extern ASM_PFX(SmiRendezvous)\r
+extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r
+extern ASM_PFX(CpuSmmDebugEntry)\r
+extern ASM_PFX(CpuSmmDebugExit)\r
+\r
+global ASM_PFX(gcStmSmiHandlerTemplate)\r
+global ASM_PFX(gcStmSmiHandlerSize)\r
+global ASM_PFX(gcStmSmiHandlerOffset)\r
+global ASM_PFX(gStmSmiCr3)\r
+global ASM_PFX(gStmSmiStack)\r
+global ASM_PFX(gStmSmbase)\r
+global ASM_PFX(gStmXdSupported)\r
+extern ASM_PFX(gStmSmiHandlerIdtr)\r
+\r
+ SECTION .text\r
+\r
+BITS 16\r
+ASM_PFX(gcStmSmiHandlerTemplate):\r
+_StmSmiEntryPoint:\r
+ mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000\r
+ mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]\r
+ dec ax\r
+ mov [cs:bx], ax\r
+ mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]\r
+ mov [cs:bx + 2], eax\r
+ mov ebp, eax ; ebp = GDT base\r
+o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
+ mov ax, PROTECT_MODE_CS\r
+ mov [cs:bx-0x2],ax\r
+ DB 0x66, 0xbf ; mov edi, SMBASE\r
+ASM_PFX(gStmSmbase): DD 0\r
+ lea eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]\r
+ mov [cs:bx-0x6],eax\r
+ mov ebx, cr0\r
+ and ebx, 0x9ffafff3\r
+ or ebx, 0x23\r
+ mov cr0, ebx\r
+ jmp dword 0x0:0x0\r
+_StmGdtDesc:\r
+ DW 0\r
+ DD 0\r
+\r
+BITS 32\r
+@32bit:\r
+ mov ax, PROTECT_MODE_DS\r
+o16 mov ds, ax\r
+o16 mov es, ax\r
+o16 mov fs, ax\r
+o16 mov gs, ax\r
+o16 mov ss, ax\r
+ DB 0xbc ; mov esp, imm32\r
+ASM_PFX(gStmSmiStack): DD 0\r
+ mov eax, ASM_PFX(gStmSmiHandlerIdtr)\r
+ lidt [eax]\r
+ jmp ProtFlatMode\r
+\r
+ProtFlatMode:\r
+ DB 0xb8 ; mov eax, imm32\r
+ASM_PFX(gStmSmiCr3): DD 0\r
+ mov cr3, eax\r
+;\r
+; Need to test for CR4 specific bit support\r
+;\r
+ mov eax, 1\r
+ cpuid ; use CPUID to determine if specific CR4 bits are supported\r
+ xor eax, eax ; Clear EAX\r
+ test edx, BIT2 ; Check for DE capabilities\r
+ jz .0\r
+ or eax, BIT3\r
+.0:\r
+ test edx, BIT6 ; Check for PAE capabilities\r
+ jz .1\r
+ or eax, BIT5\r
+.1:\r
+ test edx, BIT7 ; Check for MCE capabilities\r
+ jz .2\r
+ or eax, BIT6\r
+.2:\r
+ test edx, BIT24 ; Check for FXSR capabilities\r
+ jz .3\r
+ or eax, BIT9\r
+.3:\r
+ test edx, BIT25 ; Check for SSE capabilities\r
+ jz .4\r
+ or eax, BIT10\r
+.4: ; as cr4.PGE is not set here, refresh cr3\r
+ mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
+\r
+ cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
+ jz .6\r
+; Load TSS\r
+ mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag\r
+ mov eax, TSS_SEGMENT\r
+ ltr ax\r
+.6:\r
+\r
+; enable NXE if supported\r
+ DB 0b0h ; mov al, imm8\r
+ASM_PFX(gStmXdSupported): DB 1\r
+ cmp al, 0\r
+ jz @SkipXd\r
+;\r
+; Check XD disable bit\r
+;\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
+ jz .5\r
+ and dx, 0xFFFB ; clear XD Disable bit if it is set\r
+ wrmsr\r
+.5:\r
+ mov ecx, MSR_EFER\r
+ rdmsr\r
+ or ax, MSR_EFER_XD ; enable NXE\r
+ wrmsr\r
+ jmp @XdDone\r
+@SkipXd:\r
+ sub esp, 4\r
+@XdDone:\r
+\r
+ mov ebx, cr0\r
+ or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE\r
+ mov cr0, ebx\r
+ lea ebx, [edi + DSC_OFFSET]\r
+ mov ax, [ebx + DSC_DS]\r
+ mov ds, eax\r
+ mov ax, [ebx + DSC_OTHERSEG]\r
+ mov es, eax\r
+ mov fs, eax\r
+ mov gs, eax\r
+ mov ax, [ebx + DSC_SS]\r
+ mov ss, eax\r
+\r
+CommonHandler:\r
+ mov ebx, [esp + 4] ; CPU Index\r
+ push ebx\r
+ mov eax, ASM_PFX(CpuSmmDebugEntry)\r
+ call eax\r
+ add esp, 4\r
+\r
+ push ebx\r
+ mov eax, ASM_PFX(SmiRendezvous)\r
+ call eax\r
+ add esp, 4\r
+\r
+ push ebx\r
+ mov eax, ASM_PFX(CpuSmmDebugExit)\r
+ call eax\r
+ add esp, 4\r
+\r
+ mov eax, ASM_PFX(gStmXdSupported)\r
+ mov al, [eax]\r
+ cmp al, 0\r
+ jz .7\r
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2\r
+ jz .7\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
+ wrmsr\r
+\r
+.7:\r
+ rsm\r
+\r
+\r
+_StmSmiHandler:\r
+;\r
+; Check XD disable bit\r
+;\r
+ xor esi, esi\r
+ mov eax, ASM_PFX(gStmXdSupported)\r
+ mov al, [eax]\r
+ cmp al, 0\r
+ jz @StmXdDone\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
+ jz .5\r
+ and dx, 0xFFFB ; clear XD Disable bit if it is set\r
+ wrmsr\r
+.5:\r
+ mov ecx, MSR_EFER\r
+ rdmsr\r
+ or ax, MSR_EFER_XD ; enable NXE\r
+ wrmsr\r
+@StmXdDone:\r
+ push esi\r
+\r
+ ; below step is needed, because STM does not run above code.\r
+ ; we have to run below code to set IDT/CR0/CR4\r
+ mov eax, ASM_PFX(gStmSmiHandlerIdtr)\r
+ lidt [eax]\r
+\r
+ mov eax, cr0\r
+ or eax, 0x80010023 ; enable paging + WP + NE + MP + PE\r
+ mov cr0, eax\r
+;\r
+; Need to test for CR4 specific bit support\r
+;\r
+ mov eax, 1\r
+ cpuid ; use CPUID to determine if specific CR4 bits are supported\r
+ mov eax, cr4 ; init EAX\r
+ test edx, BIT2 ; Check for DE capabilities\r
+ jz .0\r
+ or eax, BIT3\r
+.0:\r
+ test edx, BIT6 ; Check for PAE capabilities\r
+ jz .1\r
+ or eax, BIT5\r
+.1:\r
+ test edx, BIT7 ; Check for MCE capabilities\r
+ jz .2\r
+ or eax, BIT6\r
+.2:\r
+ test edx, BIT24 ; Check for FXSR capabilities\r
+ jz .3\r
+ or eax, BIT9\r
+.3:\r
+ test edx, BIT25 ; Check for SSE capabilities\r
+ jz .4\r
+ or eax, BIT10\r
+.4: ; as cr4.PGE is not set here, refresh cr3\r
+ mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
+ ; STM init finish\r
+ jmp CommonHandler\r
+\r
+ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint\r
+ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint\r
+\r
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