/** @file\r
Implementation shared across all library instances.\r
\r
-Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) Microsoft Corporation.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;\r
UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;\r
\r
+//\r
+// Indicate SmBase for each Processors has been relocated or not. If TRUE,\r
+// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor().\r
+//\r
+BOOLEAN mSmmCpuFeaturesSmmRelocated;\r
+\r
//\r
// Set default value to assume MTRRs need to be configured on each SMI\r
//\r
//\r
mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLogicalProcessorNumber ());\r
ASSERT (mSmrrEnabled != NULL);\r
+\r
+ //\r
+ // If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded\r
+ // in the SmBase array.\r
+ //\r
+ mSmmCpuFeaturesSmmRelocated = (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) != NULL);\r
}\r
\r
/**\r
UINTN ModelId;\r
\r
//\r
- // Configure SMBASE.\r
+ // No need to configure SMBASE if SmBase relocation has been done.\r
//\r
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
- CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
+ if (!mSmmCpuFeaturesSmmRelocated) {\r
+ //\r
+ // Configure SMBASE.\r
+ //\r
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+ CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
+ }\r
\r
//\r
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r