UefiCpuPkg/SmmFeatureLib: Check SmmFeatureControl by Code_Access_Chk

[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 0c1610d9777cf2bc3bbbfda015130fb959e587e3..b839d3192f563c263f5dfe893e212039ae7b0276 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -35,6 +35,12 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define    EFI_MSR_SMRR_PHYS_MASK_VALID            BIT11\r
 #define  SMM_FEATURES_LIB_SMM_FEATURE_CONTROL      0x4E0\r
 \r
+//\r
+// MSRs required for configuration of SMM Code Access Check\r
+//\r
+#define SMM_FEATURES_LIB_IA32_MCA_CAP              0x17D\r
+#define   SMM_CODE_ACCESS_CHK_BIT                  BIT58\r
+\r
 //\r
 // Set default value to assume SMRR is not supported\r
 //\r
@@ -131,20 +137,6 @@ SmmCpuFeaturesLibConstructor (
     }\r
   }\r
 \r
-  //\r
-  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
-  // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
-  // Processor Family\r
-  //\r
-  // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
-  // Intel(R) Core(TM) Processor Family MSRs\r
-  //\r
-  if (FamilyId == 0x06) {\r
-    if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
-      mSmmFeatureControlSupported = TRUE;\r
-    }\r
-  }\r
-\r
   //\r
   // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
   // Volume 3C, Section 34.4.2 SMRAM Caching\r
@@ -214,6 +206,10 @@ SmmCpuFeaturesInitializeProcessor (
 {\r
   SMRAM_SAVE_STATE_MAP  *CpuState;\r
   UINT64                FeatureControl;\r
+  UINT32                RegEax;\r
+  UINT32                RegEdx;\r
+  UINTN                 FamilyId;\r
+  UINTN                 ModelId;\r
 \r
   //\r
   // Configure SMBASE.\r
@@ -253,6 +249,36 @@ SmmCpuFeaturesInitializeProcessor (
     AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
     mSmrrEnabled[CpuIndex] = FALSE;\r
   }\r
+\r
+  //\r
+  // Retrieve CPU Family and Model\r
+  //\r
+  AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
+  FamilyId = (RegEax >> 8) & 0xf;\r
+  ModelId  = (RegEax >> 4) & 0xf;\r
+  if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+    ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
+  }\r
+\r
+  //\r
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+  // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
+  // Processor Family.\r
+  //\r
+  // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
+  // Intel(R) Core(TM) Processor Family MSRs.\r
+  //\r
+  if (FamilyId == 0x06) {\r
+    if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
+      //\r
+      // Check to see if the CPU supports the SMM Code Access Check feature\r
+      // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
+      //\r
+      if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {\r
+        mSmmFeatureControlSupported = TRUE;\r
+      }\r
+    }\r
+  }\r
 }\r
 \r
 /**\r