UefiCpuPkg/SmmCpuFeaturesLib: Fix coding style issues

[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 3e480e1761fd4709db128794156d9bcb92349498..079baa4ae19f516e1e0e3a297ea1ea3e99871763 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -1,7 +1,7 @@
 /** @file\r
 The CPU specific programming for PiSmmCpuDxeSmm module.\r
 \r
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -41,6 +41,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define SMM_FEATURES_LIB_IA32_MCA_CAP              0x17D\r
 #define   SMM_CODE_ACCESS_CHK_BIT                  BIT58\r
 \r
+/**\r
+  Internal worker function that is called to complete CPU initialization at the\r
+  end of SmmCpuFeaturesInitializeProcessor().\r
+\r
+**/\r
+VOID\r
+FinishSmmCpuFeaturesInitializeProcessor (\r
+  VOID\r
+  );\r
+\r
 //\r
 // Set default value to assume SMRR is not supported\r
 //\r
@@ -245,9 +255,26 @@ SmmCpuFeaturesInitializeProcessor (
   // is protected and the normal mode code execution will fail.\r
   //\r
   if (mSmrrSupported) {\r
-    AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
-    AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
-    mSmrrEnabled[CpuIndex] = FALSE;\r
+    //\r
+    // SMRR size cannot be less than 4-KBytes\r
+    // SMRR size must be of length 2^n\r
+    // SMRR base alignment cannot be less than SMRR length\r
+    //\r
+    if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
+        (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
+        ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
+      //\r
+      // Print message and halt if CPU is Monarch\r
+      //\r
+      if (IsMonarch) {\r
+        DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
+        CpuDeadLoop ();\r
+      }\r
+    } else {\r
+      AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
+      AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
+      mSmrrEnabled[CpuIndex] = FALSE;\r
+    }\r
   }\r
 \r
   //\r
@@ -279,6 +306,11 @@ SmmCpuFeaturesInitializeProcessor (
       }\r
     }\r
   }\r
+\r
+  //\r
+  //  Call internal worker function that completes the CPU initialization\r
+  //\r
+  FinishSmmCpuFeaturesInitializeProcessor ();\r
 }\r
 \r
 /**\r
@@ -339,66 +371,6 @@ SmmCpuFeaturesSmmRelocationComplete (
 {\r
 }\r
 \r
-/**\r
-  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is\r
-  returned, then a custom SMI handler is not provided by this library,\r
-  and the default SMI handler must be used.\r
-\r
-  @retval 0    Use the default SMI handler.\r
-  @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
-               The caller is required to allocate enough SMRAM for each CPU to\r
-               support the size of the custom SMI handler.\r
-**/\r
-UINTN\r
-EFIAPI\r
-SmmCpuFeaturesGetSmiHandlerSize (\r
-  VOID\r
-  )\r
-{\r
-  return 0;\r
-}\r
-\r
-/**\r
-  Install a custom SMI handler for the CPU specified by CpuIndex.  This function\r
-  is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
-  than zero and is called by the CPU that was elected as monarch during System\r
-  Management Mode initialization.\r
-\r
-  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.\r
-                        The value must be between 0 and the NumberOfCpus field\r
-                        in the System Management System Table (SMST).\r
-  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.\r
-  @param[in] SmiStack   The stack to use when an SMI is processed by the\r
-                        the CPU specified by CpuIndex.\r
-  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is\r
-                        processed by the CPU specified by CpuIndex.\r
-  @param[in] GdtBase    The base address of the GDT to use when an SMI is\r
-                        processed by the CPU specified by CpuIndex.\r
-  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is\r
-                        processed by the CPU specified by CpuIndex.\r
-  @param[in] IdtBase    The base address of the IDT to use when an SMI is\r
-                        processed by the CPU specified by CpuIndex.\r
-  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is\r
-                        processed by the CPU specified by CpuIndex.\r
-  @param[in] Cr3        The base address of the page tables to use when an SMI\r
-                        is processed by the CPU specified by CpuIndex.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesInstallSmiHandler (\r
-  IN UINTN   CpuIndex,\r
-  IN UINT32  SmBase,\r
-  IN VOID    *SmiStack,\r
-  IN UINTN   StackSize,\r
-  IN UINTN   GdtBase,\r
-  IN UINTN   GdtSize,\r
-  IN UINTN   IdtBase,\r
-  IN UINTN   IdtSize,\r
-  IN UINT32  Cr3\r
-  )\r
-{\r
-}\r
-\r
 /**\r
   Determines if MTRR registers must be configured to set SMRAM cache-ability\r
   when executing in System Management Mode.\r