/** @file\r
The CPU specific programming for PiSmmCpuDxeSmm module.\r
\r
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0\r
\r
+//\r
+// MSRs required for configuration of SMM Code Access Check\r
+//\r
+#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
+#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
+\r
//\r
// Set default value to assume SMRR is not supported\r
//\r
}\r
}\r
\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
- // Processor Family\r
- //\r
- // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
- // Intel(R) Core(TM) Processor Family MSRs\r
- //\r
- if (FamilyId == 0x06) {\r
- if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
- mSmmFeatureControlSupported = TRUE;\r
- }\r
- }\r
-\r
//\r
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
// Volume 3C, Section 34.4.2 SMRAM Caching\r
{\r
SMRAM_SAVE_STATE_MAP *CpuState;\r
UINT64 FeatureControl;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINTN FamilyId;\r
+ UINTN ModelId;\r
\r
//\r
// Configure SMBASE.\r
// is protected and the normal mode code execution will fail.\r
//\r
if (mSmrrSupported) {\r
- AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
- mSmrrEnabled[CpuIndex] = FALSE;\r
+ //\r
+ // SMRR size cannot be less than 4-KBytes\r
+ // SMRR size must be of length 2^n\r
+ // SMRR base alignment cannot be less than SMRR length\r
+ //\r
+ if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
+ (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
+ ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
+ //\r
+ // Print message and halt if CPU is Monarch\r
+ //\r
+ if (IsMonarch) {\r
+ DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
+ CpuDeadLoop ();\r
+ }\r
+ } else {\r
+ AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
+ mSmrrEnabled[CpuIndex] = FALSE;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Retrieve CPU Family and Model\r
+ //\r
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
+ FamilyId = (RegEax >> 8) & 0xf;\r
+ ModelId = (RegEax >> 4) & 0xf;\r
+ if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+ ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
+ }\r
+\r
+ //\r
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
+ // Processor Family.\r
+ //\r
+ // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
+ // Intel(R) Core(TM) Processor Family MSRs.\r
+ //\r
+ if (FamilyId == 0x06) {\r
+ if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
+ //\r
+ // Check to see if the CPU supports the SMM Code Access Check feature\r
+ // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
+ //\r
+ if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {\r
+ mSmmFeatureControlSupported = TRUE;\r
+ }\r
+ }\r
}\r
}\r
\r
{\r
return EFI_UNSUPPORTED;\r
}\r
+\r
+/**\r
+ This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
+ notification is completely processed.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesCompleteSmmReadyToLock (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ This API provides a method for a CPU to allocate a specific region for storing page tables.\r
+\r
+ This API can be called more once to allocate memory for page tables.\r
+\r
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
+ returned.\r
+\r
+ This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+ @param Pages The number of 4 KB pages to allocate.\r
+\r
+ @return A pointer to the allocated buffer for page tables.\r
+ @retval NULL Fail to allocate a specific region for storing page tables,\r
+ Or there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+SmmCpuFeaturesAllocatePageTableMemory (\r
+ IN UINTN Pages\r
+ )\r
+{\r
+ return NULL;\r
+}\r
+\r
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