/** @file\r
The CPU specific programming for PiSmmCpuDxeSmm module.\r
\r
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1\r
#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
+#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0\r
+\r
+//\r
+// MSRs required for configuration of SMM Code Access Check\r
+//\r
+#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
+#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
+\r
+/**\r
+ Internal worker function that is called to complete CPU initialization at the\r
+ end of SmmCpuFeaturesInitializeProcessor().\r
+\r
+**/\r
+VOID\r
+FinishSmmCpuFeaturesInitializeProcessor (\r
+ VOID\r
+ );\r
\r
//\r
// Set default value to assume SMRR is not supported\r
//\r
BOOLEAN mSmrrSupported = FALSE;\r
\r
+//\r
+// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported\r
+//\r
+BOOLEAN mSmmFeatureControlSupported = FALSE;\r
+\r
//\r
// Set default value to assume IA-32 Architectural MSRs are used\r
//\r
{\r
SMRAM_SAVE_STATE_MAP *CpuState;\r
UINT64 FeatureControl;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINTN FamilyId;\r
+ UINTN ModelId;\r
\r
//\r
// Configure SMBASE.\r
// is protected and the normal mode code execution will fail.\r
//\r
if (mSmrrSupported) {\r
- AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
- mSmrrEnabled[CpuIndex] = FALSE;\r
+ //\r
+ // SMRR size cannot be less than 4-KBytes\r
+ // SMRR size must be of length 2^n\r
+ // SMRR base alignment cannot be less than SMRR length\r
+ //\r
+ if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
+ (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
+ ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
+ //\r
+ // Print message and halt if CPU is Monarch\r
+ //\r
+ if (IsMonarch) {\r
+ DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
+ CpuDeadLoop ();\r
+ }\r
+ } else {\r
+ AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
+ mSmrrEnabled[CpuIndex] = FALSE;\r
+ }\r
}\r
+\r
+ //\r
+ // Retrieve CPU Family and Model\r
+ //\r
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
+ FamilyId = (RegEax >> 8) & 0xf;\r
+ ModelId = (RegEax >> 4) & 0xf;\r
+ if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+ ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
+ }\r
+\r
+ //\r
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
+ // Processor Family.\r
+ //\r
+ // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
+ // Intel(R) Core(TM) Processor Family MSRs.\r
+ //\r
+ if (FamilyId == 0x06) {\r
+ if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||\r
+ ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F ||\r
+ ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C) {\r
+ //\r
+ // Check to see if the CPU supports the SMM Code Access Check feature\r
+ // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
+ //\r
+ if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {\r
+ mSmmFeatureControlSupported = TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Call internal worker function that completes the CPU initialization\r
+ //\r
+ FinishSmmCpuFeaturesInitializeProcessor ();\r
}\r
\r
/**\r
{\r
}\r
\r
-/**\r
- Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
- returned, then a custom SMI handler is not provided by this library,\r
- and the default SMI handler must be used.\r
-\r
- @retval 0 Use the default SMI handler.\r
- @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
- The caller is required to allocate enough SMRAM for each CPU to\r
- support the size of the custom SMI handler.\r
-**/\r
-UINTN\r
-EFIAPI\r
-SmmCpuFeaturesGetSmiHandlerSize (\r
- VOID\r
- )\r
-{\r
- return 0;\r
-}\r
-\r
-/**\r
- Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
- is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
- than zero and is called by the CPU that was elected as monarch during System\r
- Management Mode initialization.\r
-\r
- @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
- The value must be between 0 and the NumberOfCpus field\r
- in the System Management System Table (SMST).\r
- @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
- @param[in] SmiStack The stack to use when an SMI is processed by the\r
- the CPU specified by CpuIndex.\r
- @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
- processed by the CPU specified by CpuIndex.\r
- @param[in] GdtBase The base address of the GDT to use when an SMI is\r
- processed by the CPU specified by CpuIndex.\r
- @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
- processed by the CPU specified by CpuIndex.\r
- @param[in] IdtBase The base address of the IDT to use when an SMI is\r
- processed by the CPU specified by CpuIndex.\r
- @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
- processed by the CPU specified by CpuIndex.\r
- @param[in] Cr3 The base address of the page tables to use when an SMI\r
- is processed by the CPU specified by CpuIndex.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesInstallSmiHandler (\r
- IN UINTN CpuIndex,\r
- IN UINT32 SmBase,\r
- IN VOID *SmiStack,\r
- IN UINTN StackSize,\r
- IN UINTN GdtBase,\r
- IN UINTN GdtSize,\r
- IN UINTN IdtBase,\r
- IN UINTN IdtSize,\r
- IN UINT32 Cr3\r
- )\r
-{\r
-}\r
-\r
/**\r
Determines if MTRR registers must be configured to set SMRAM cache-ability\r
when executing in System Management Mode.\r
IN SMM_REG_NAME RegName\r
)\r
{\r
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+ return TRUE;\r
+ }\r
return FALSE;\r
}\r
\r
IN SMM_REG_NAME RegName\r
)\r
{\r
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+ return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
+ }\r
return 0;\r
}\r
\r
IN UINT64 Value\r
)\r
{\r
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+ AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
+ }\r
}\r
\r
/**\r
{\r
return EFI_UNSUPPORTED;\r
}\r
+\r
+/**\r
+ This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
+ notification is completely processed.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesCompleteSmmReadyToLock (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ This API provides a method for a CPU to allocate a specific region for storing page tables.\r
+\r
+ This API can be called more once to allocate memory for page tables.\r
+\r
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
+ returned.\r
+\r
+ This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+ @param Pages The number of 4 KB pages to allocate.\r
+\r
+ @return A pointer to the allocated buffer for page tables.\r
+ @retval NULL Fail to allocate a specific region for storing page tables,\r
+ Or there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+SmmCpuFeaturesAllocatePageTableMemory (\r
+ IN UINTN Pages\r
+ )\r
+{\r
+ return NULL;\r
+}\r
+\r
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