--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# SmiException.S\r
+#\r
+# Abstract:\r
+#\r
+# Exception handlers used in SM mode\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(gcStmPsd)\r
+\r
+ASM_GLOBAL ASM_PFX(SmmStmExceptionHandler)\r
+ASM_GLOBAL ASM_PFX(SmmStmSetup)\r
+ASM_GLOBAL ASM_PFX(SmmStmTeardown)\r
+\r
+.equ CODE_SEL, 0x38\r
+.equ DATA_SEL, 0x20\r
+.equ TR_SEL, 0x40\r
+\r
+.equ MSR_IA32_MISC_ENABLE, 0x1A0\r
+.equ MSR_EFER, 0x0c0000080\r
+.equ MSR_EFER_XD, 0x0800\r
+\r
+ .data\r
+\r
+#\r
+# This structure serves as a template for all processors.\r
+#\r
+ASM_PFX(gcStmPsd):\r
+ .ascii "TXTPSSIG"\r
+ .word PSD_SIZE\r
+ .word 1 # Version\r
+ .long 0 # LocalApicId\r
+ .byte 0xF # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
+ .byte 0 # BIOS to STM\r
+ .byte 0 # STM to BIOS\r
+ .byte 0\r
+ .word CODE_SEL\r
+ .word DATA_SEL\r
+ .word DATA_SEL\r
+ .word DATA_SEL\r
+ .word TR_SEL\r
+ .word 0\r
+ .quad 0 # SmmCr3\r
+ .quad ASM_PFX(_OnStmSetup)\r
+ .quad ASM_PFX(_OnStmTeardown)\r
+ .quad 0 # SmmSmiHandlerRip - SMM guest entrypoint\r
+ .quad 0 # SmmSmiHandlerRsp\r
+ .quad 0\r
+ .long 0\r
+ .long 0x80010100 # RequiredStmSmmRevId\r
+ .quad ASM_PFX(_OnException)\r
+ .quad 0 # ExceptionStack\r
+ .word DATA_SEL\r
+ .word 0x1F # ExceptionFilter\r
+ .long 0\r
+ .quad 0\r
+ .quad 0 # BiosHwResourceRequirementsPtr\r
+ .quad 0 # AcpiRsdp\r
+ .byte 0 # PhysicalAddressBits\r
+.equ PSD_SIZE, . - ASM_PFX(gcStmPsd)\r
+\r
+ .text\r
+#------------------------------------------------------------------------------\r
+# SMM Exception handlers\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(_OnException)\r
+ASM_PFX(_OnException):\r
+ movq %rsp, %rcx\r
+ subq $0x28, %rsp\r
+ call ASM_PFX(SmmStmExceptionHandler)\r
+ addq $0x28, %rsp\r
+ movl %eax, %ebx\r
+ movl $4, %eax\r
+ .byte 0xf, 0x1, 0xc1 # VMCALL\r
+ jmp .\r
+\r
+ASM_GLOBAL ASM_PFX(_OnStmSetup)\r
+ASM_PFX(_OnStmSetup):\r
+#\r
+# Check XD disable bit\r
+#\r
+ xorq %r8, %r8\r
+ movabsq $ASM_PFX(gStmXdSupported), %rax\r
+ movb (%rax), %al\r
+ cmpb $0, %al\r
+ jz StmXdDone1\r
+ movl $MSR_IA32_MISC_ENABLE, %ecx\r
+ rdmsr\r
+ movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]\r
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]\r
+ jz L13\r
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set\r
+ wrmsr\r
+L13:\r
+ movl $MSR_EFER, %ecx\r
+ rdmsr\r
+ orw $MSR_EFER_XD,%ax # enable NXE\r
+ wrmsr\r
+StmXdDone1:\r
+ pushq %r8\r
+\r
+ subq $0x20, %rsp\r
+ call ASM_PFX(SmmStmSetup)\r
+ addq 0x20, %rsp\r
+\r
+ movabsq $ASM_PFX(gStmXdSupported), %rax\r
+ movb (%rax), %al\r
+ cmpb $0, %al\r
+ jz L14\r
+ popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]\r
+ testl $BIT2, %edx\r
+ jz L14\r
+ movl $MSR_IA32_MISC_ENABLE, %ecx\r
+ rdmsr\r
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM\r
+ wrmsr\r
+L14:\r
+\r
+ rsm\r
+\r
+ASM_GLOBAL ASM_PFX(_OnStmTeardown)\r
+ASM_PFX(_OnStmTeardown):\r
+#\r
+# Check XD disable bit\r
+#\r
+ xorq %r8, %r8\r
+ movabsq $ASM_PFX(gStmXdSupported), %rax\r
+ movb (%rax), %al\r
+ cmpb $0, %al\r
+ jz StmXdDone2\r
+ movl $MSR_IA32_MISC_ENABLE, %ecx\r
+ rdmsr\r
+ movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]\r
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]\r
+ jz L15\r
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set\r
+ wrmsr\r
+L15:\r
+ movl $MSR_EFER, %ecx\r
+ rdmsr\r
+ orw $MSR_EFER_XD,%ax # enable NXE\r
+ wrmsr\r
+StmXdDone2:\r
+ pushq %r8\r
+\r
+ subq $0x20, %rsp\r
+ call ASM_PFX(SmmStmTeardown)\r
+ addq $0x20, %rsp\r
+\r
+ movabsq $ASM_PFX(gStmXdSupported), %rax\r
+ movb (%rax), %al\r
+ cmpb $0, %al\r
+ jz L16\r
+ popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]\r
+ testl $BIT2, %edx\r
+ jz L16\r
+ movl $MSR_IA32_MISC_ENABLE, %ecx\r
+ rdmsr\r
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM\r
+ wrmsr\r
+L16:\r
+\r
+ rsm\r
+\r
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