UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / PageTbl.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 2483f2ea849d44c0f915a9e5c6b1a19c38f9f61e..9c8e2d15ac46a9d2bf3e153d959273682db53b34 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -28,6 +28,26 @@ EnableCet (
   VOID\r
   );\r
 \r
+/**\r
+  Get page table base address and the depth of the page table.\r
+\r
+  @param[out] Base        Page table base address.\r
+  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level paging.\r
+**/\r
+VOID\r
+GetPageTable (\r
+  OUT UINTN   *Base,\r
+  OUT BOOLEAN *FiveLevels OPTIONAL\r
+  )\r
+{\r
+  *Base = ((mInternalCr3 == 0) ?\r
+            (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :\r
+            mInternalCr3);\r
+  if (FiveLevels != NULL) {\r
+    *FiveLevels = FALSE;\r
+  }\r
+}\r
+\r
 /**\r
   Create PageTable for SMM use.\r
 \r
@@ -226,6 +246,7 @@ SetPageTableAttributes (
   UINT64                *L1PageTable;\r
   UINT64                *L2PageTable;\r
   UINT64                *L3PageTable;\r
+  UINTN                 PageTableBase;\r
   BOOLEAN               IsSplitted;\r
   BOOLEAN               PageTableSplitted;\r
   BOOLEAN               CetEnabled;\r
@@ -268,9 +289,10 @@ SetPageTableAttributes (
     DEBUG ((DEBUG_INFO, "Start...\n"));\r
     PageTableSplitted = FALSE;\r
 \r
-    L3PageTable = (UINT64 *)GetPageTableBase ();\r
+    GetPageTable (&PageTableBase, NULL);\r
+    L3PageTable = (UINT64 *)PageTableBase;\r
 \r
-    SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
+    SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
     PageTableSplitted = (PageTableSplitted || IsSplitted);\r
 \r
     for (Index3 = 0; Index3 < 4; Index3++) {\r