Always set WP in CR0.

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.S

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index fbaa0725f0bc8baf3633fc2bc2e36ac6be66f9ee..ec5b9a0b04231affd66d7a04c661625199048343 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -123,7 +123,7 @@ L11:
 L12:                                       # as cr4.PGE is not set here, refresh cr3\r
     movl    %eax, %cr4                     # in PreModifyMtrrs() to flush TLB.\r
     movl    %cr0, %ebx\r
-    orl     $0x080000000, %ebx             # enable paging\r
+    orl     $0x080010000, %ebx             # enable paging + WP\r
     movl    %ebx, %cr0\r
     leal    DSC_OFFSET(%edi),%ebx\r
     movw    DSC_DS(%ebx),%ax\r