MdePkg/BaseLib: add PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.asm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
index b628fe8bd88c233873815f9a68bd55baba085bd9..8296f36d26381fef25dbd83f39e8c35cdac72d48 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -22,6 +22,13 @@
     .model  flat,C\r
     .xmm\r
 \r
+MSR_IA32_MISC_ENABLE  EQU     1A0h\r
+MSR_EFER      EQU     0c0000080h\r
+MSR_EFER_XD   EQU     0800h\r
+\r
+;\r
+; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
+;\r
 DSC_OFFSET    EQU     0fb00h\r
 DSC_GDTPTR    EQU     30h\r
 DSC_GDTSIZ    EQU     38h\r
@@ -34,14 +41,16 @@ PROTECT_MODE_CS EQU   08h
 PROTECT_MODE_DS EQU   20h\r
 TSS_SEGMENT     EQU   40h\r
 \r
-SmiRendezvous   PROTO   C\r
+SmiRendezvous      PROTO   C\r
+CpuSmmDebugEntry   PROTO   C\r
+CpuSmmDebugExit    PROTO   C\r
 \r
 EXTERNDEF   gcSmiHandlerTemplate:BYTE\r
 EXTERNDEF   gcSmiHandlerSize:WORD\r
 EXTERNDEF   gSmiCr3:DWORD\r
 EXTERNDEF   gSmiStack:DWORD\r
 EXTERNDEF   gSmbase:DWORD\r
-EXTERNDEF   FeaturePcdGet (PcdCpuSmmDebug):BYTE\r
+EXTERNDEF   mXdSupported:BYTE\r
 EXTERNDEF   FeaturePcdGet (PcdCpuSmmStackGuard):BYTE\r
 EXTERNDEF   gSmiHandlerIdtr:FWORD\r
 \r
@@ -127,8 +136,42 @@ gSmiCr3     DD      ?
     or      eax, BIT10\r
 @@:                                     ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.\r
+\r
+    cmp     FeaturePcdGet (PcdCpuSmmStackGuard), 0\r
+    jz      @F\r
+; Load TSS\r
+    mov     byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r
+    mov     eax, TSS_SEGMENT\r
+    ltr     ax\r
+@@:\r
+\r
+; enable NXE if supported\r
+    DB      0b0h                        ; mov al, imm8\r
+mXdSupported     DB      1\r
+    cmp     al, 0\r
+    jz      @SkipXd\r
+;\r
+; Check XD disable bit\r
+;\r
+    mov     ecx, MSR_IA32_MISC_ENABLE\r
+    rdmsr\r
+    push    edx                        ; save MSR_IA32_MISC_ENABLE[63-32]\r
+    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]\r
+    jz      @f\r
+    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set\r
+    wrmsr\r
+@@:\r
+    mov     ecx, MSR_EFER\r
+    rdmsr\r
+    or      ax, MSR_EFER_XD             ; enable NXE\r
+    wrmsr\r
+    jmp     @XdDone\r
+@SkipXd:\r
+    sub     esp, 4\r
+@XdDone:\r
+\r
     mov     ebx, cr0\r
-    or      ebx, 080000000h             ; enable paging\r
+    or      ebx, 080010023h             ; enable paging + WP + NE + MP + PE\r
     mov     cr0, ebx\r
     lea     ebx, [edi + DSC_OFFSET]\r
     mov     ax, [ebx + DSC_DS]\r
@@ -140,51 +183,38 @@ gSmiCr3     DD      ?
     mov     ax, [ebx + DSC_SS]\r
     mov     ss, eax\r
 \r
-    cmp     FeaturePcdGet (PcdCpuSmmStackGuard), 0\r
-    jz      @F\r
-\r
-; Load TSS\r
-    mov     byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r
-    mov     eax, TSS_SEGMENT\r
-    ltr     ax\r
-@@:\r
 ;   jmp     _SmiHandler                 ; instruction is not needed\r
 \r
 _SmiHandler PROC\r
-    cmp     FeaturePcdGet (PcdCpuSmmDebug), 0\r
-    jz      @3\r
-    call    @1\r
-@1:\r
-    pop     ebp\r
-    mov     eax, 80000001h\r
-    cpuid\r
-    bt      edx, 29                     ; check cpuid to identify X64 or IA32\r
-    lea     edi, [ebp - (@1 - _SmiEntryPoint) + 7fc8h]\r
-    lea     esi, [edi + 4]\r
-    jnc     @2\r
-    add     esi, 4\r
-@2:\r
-    mov     ecx, [esi]\r
-    mov     edx, [edi]\r
-@5:\r
-    mov     dr6, ecx\r
-    mov     dr7, edx                    ; restore DR6 & DR7 before running C code\r
-@3:\r
-    mov     ecx, [esp]                  ; CPU Index\r
-\r
-    push    ecx\r
+    mov     ebx, [esp + 4]                  ; CPU Index\r
+    push    ebx\r
+    mov     eax, CpuSmmDebugEntry\r
+    call    eax\r
+    add     esp, 4\r
+\r
+    push    ebx\r
     mov     eax, SmiRendezvous\r
     call    eax\r
-    pop     ecx\r
+    add     esp, 4\r
+\r
+    push    ebx\r
+    mov     eax, CpuSmmDebugExit\r
+    call    eax\r
+    add     esp, 4\r
 \r
-    cmp     FeaturePcdGet (PcdCpuSmmDebug), 0\r
-    jz      @4\r
+    mov     eax, offset mXdSupported\r
+    mov     al, [eax]\r
+    cmp     al, 0\r
+    jz      @f\r
+    pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
+    test    edx, BIT2\r
+    jz      @f\r
+    mov     ecx, MSR_IA32_MISC_ENABLE\r
+    rdmsr\r
+    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM\r
+    wrmsr\r
 \r
-    mov     ecx, dr6\r
-    mov     edx, dr7\r
-    mov     [esi], ecx\r
-    mov     [edi], edx\r
-@4:\r
+@@:\r
     rsm\r
 _SmiHandler ENDP\r
 \r