+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# SmiException.S\r
-#\r
-# Abstract:\r
-#\r
-# Exception handlers used in SM mode\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(SmiPFHandler)\r
-ASM_GLOBAL ASM_PFX(PageFaultStubFunction)\r
-ASM_GLOBAL ASM_PFX(gcSmiIdtr)\r
-ASM_GLOBAL ASM_PFX(gcSmiGdtr)\r
-ASM_GLOBAL ASM_PFX(gTaskGateDescriptor)\r
-ASM_GLOBAL ASM_PFX(gcPsd)\r
-ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))\r
-\r
- .data\r
-\r
-NullSeg: .quad 0 # reserved by architecture\r
-CodeSeg32:\r
- .word -1 # LimitLow\r
- .word 0 # BaseLow\r
- .byte 0 # BaseMid\r
- .byte 0x9b\r
- .byte 0xcf # LimitHigh\r
- .byte 0 # BaseHigh\r
-ProtModeCodeSeg32:\r
- .word -1 # LimitLow\r
- .word 0 # BaseLow\r
- .byte 0 # BaseMid\r
- .byte 0x9b\r
- .byte 0xcf # LimitHigh\r
- .byte 0 # BaseHigh\r
-ProtModeSsSeg32:\r
- .word -1 # LimitLow\r
- .word 0 # BaseLow\r
- .byte 0 # BaseMid\r
- .byte 0x93\r
- .byte 0xcf # LimitHigh\r
- .byte 0 # BaseHigh\r
-DataSeg32:\r
- .word -1 # LimitLow\r
- .word 0 # BaseLow\r
- .byte 0 # BaseMid\r
- .byte 0x93\r
- .byte 0xcf # LimitHigh\r
- .byte 0 # BaseHigh\r
-CodeSeg16:\r
- .word -1\r
- .word 0\r
- .byte 0\r
- .byte 0x9b\r
- .byte 0x8f\r
- .byte 0\r
-DataSeg16:\r
- .word -1\r
- .word 0\r
- .byte 0\r
- .byte 0x93\r
- .byte 0x8f\r
- .byte 0\r
-CodeSeg64:\r
- .word -1 # LimitLow\r
- .word 0 # BaseLow\r
- .byte 0 # BaseMid\r
- .byte 0x9b\r
- .byte 0xaf # LimitHigh\r
- .byte 0 # BaseHigh\r
-.equ GDT_SIZE, .- NullSeg\r
-\r
-TssSeg:\r
- .word TSS_DESC_SIZE -1 # LimitLow\r
- .word 0 # BaseLow\r
- .byte 0 # BaseMid\r
- .byte 0x89\r
- .byte 0x00 # LimitHigh\r
- .byte 0 # BaseHigh\r
-ExceptionTssSeg:\r
- .word TSS_DESC_SIZE - 1 # LimitLow\r
- .word 0 # BaseLow\r
- .byte 0 # BaseMid\r
- .byte 0x89\r
- .byte 0x00 # LimitHigh\r
- .byte 0 # BaseHigh\r
-\r
-.equ CODE_SEL, CodeSeg32 - NullSeg\r
-.equ DATA_SEL, DataSeg32 - NullSeg\r
-.equ TSS_SEL, TssSeg - NullSeg\r
-.equ EXCEPTION_TSS_SEL, ExceptionTssSeg - NullSeg\r
-\r
-# IA32 TSS fields\r
-.equ TSS_ESP0, 4\r
-.equ TSS_SS0, 8\r
-.equ TSS_ESP1, 12\r
-.equ TSS_SS1, 16\r
-.equ TSS_ESP2, 20\r
-.equ TSS_SS2, 24\r
-.equ TSS_CR3, 28\r
-.equ TSS_EIP, 32\r
-.equ TSS_EFLAGS, 36\r
-.equ TSS_EAX, 40\r
-.equ TSS_ECX, 44\r
-.equ TSS_EDX, 48\r
-.equ TSS_EBX, 52\r
-.equ TSS_ESP, 56\r
-.equ TSS_EBP, 60\r
-.equ TSS_ESI, 64\r
-.equ TSS_EDI, 68\r
-.equ TSS_ES, 72\r
-.equ TSS_CS, 76\r
-.equ TSS_SS, 80\r
-.equ TSS_DS, 84\r
-.equ TSS_FS, 88\r
-.equ TSS_GS, 92\r
-.equ TSS_LDT, 96\r
-\r
-# Create 2 TSS segments just after GDT\r
-TssDescriptor:\r
- .word 0 # PreviousTaskLink\r
- .word 0 # Reserved\r
- .long 0 # ESP0\r
- .word 0 # SS0\r
- .word 0 # Reserved\r
- .long 0 # ESP1\r
- .word 0 # SS1\r
- .word 0 # Reserved\r
- .long 0 # ESP2\r
- .word 0 # SS2\r
- .word 0 # Reserved\r
- .long 0 # CR3\r
- .long 0 # EIP\r
- .long 0 # EFLAGS\r
- .long 0 # EAX\r
- .long 0 # ECX\r
- .long 0 # EDX\r
- .long 0 # EBX\r
- .long 0 # ESP\r
- .long 0 # EBP\r
- .long 0 # ESI\r
- .long 0 # EDI\r
- .word 0 # ES\r
- .word 0 # Reserved\r
- .word 0 # CS\r
- .word 0 # Reserved\r
- .word 0 # SS\r
- .word 0 # Reserved\r
- .word 0 # DS\r
- .word 0 # Reserved\r
- .word 0 # FS\r
- .word 0 # Reserved\r
- .word 0 # GS\r
- .word 0 # Reserved\r
- .word 0 # LDT Selector\r
- .word 0 # Reserved\r
- .word 0 # T\r
- .word 0 # I/O Map Base\r
-.equ TSS_DESC_SIZE, . - TssDescriptor\r
-\r
-ExceptionTssDescriptor:\r
- .word 0 # PreviousTaskLink\r
- .word 0 # Reserved\r
- .long 0 # ESP0\r
- .word 0 # SS0\r
- .word 0 # Reserved\r
- .long 0 # ESP1\r
- .word 0 # SS1\r
- .word 0 # Reserved\r
- .long 0 # ESP2\r
- .word 0 # SS2\r
- .word 0 # Reserved\r
- .long 0 # CR3\r
- .long PFHandlerEntry # EIP\r
- .long 00000002 # EFLAGS\r
- .long 0 # EAX\r
- .long 0 # ECX\r
- .long 0 # EDX\r
- .long 0 # EBX\r
- .long 0 # ESP\r
- .long 0 # EBP\r
- .long 0 # ESI\r
- .long 0 # EDI\r
- .word DATA_SEL # ES\r
- .word 0 # Reserved\r
- .word CODE_SEL # CS\r
- .word 0 # Reserved\r
- .word DATA_SEL # SS\r
- .word 0 # Reserved\r
- .word DATA_SEL # DS\r
- .word 0 # Reserved\r
- .word DATA_SEL # FS\r
- .word 0 # Reserved\r
- .word DATA_SEL # GS\r
- .word 0 # Reserved\r
- .word 0 # LDT Selector\r
- .word 0 # Reserved\r
- .word 0 # T\r
- .word 0 # I/O Map Base\r
-\r
-ASM_PFX(gcPsd):\r
- .ascii "PSDSIG "\r
- .word PSD_SIZE\r
- .word 2\r
- .word 1 << 2\r
- .word CODE_SEL\r
- .word DATA_SEL\r
- .word DATA_SEL\r
- .word DATA_SEL\r
- .word 0\r
- .long 0\r
- .long 0\r
- .long 0\r
- .long 0\r
- .quad 0\r
- .long NullSeg\r
- .long 0\r
- .long GDT_SIZE\r
- .long 0\r
- .space 24, 0\r
- .long 0\r
- .long 0\r
-.equ PSD_SIZE, . - ASM_PFX(gcPsd)\r
-\r
-ASM_PFX(gcSmiGdtr): .word GDT_SIZE - 1\r
- .long NullSeg\r
-\r
-ASM_PFX(gcSmiIdtr): .word 0\r
- .long 0\r
-\r
-ASM_PFX(gTaskGateDescriptor):\r
- .word 0 # Reserved\r
- .word EXCEPTION_TSS_SEL # TSS Segment selector\r
- .byte 0 # Reserved\r
- .byte 0x85 # Task Gate, present, DPL = 0\r
- .word 0 # Reserved\r
-\r
- .text\r
-\r
-#------------------------------------------------------------------------------\r
-# PageFaultIdtHandlerSmmProfile is the entry point for all exceptions\r
-#\r
-# Stack:\r
-#+---------------------+\r
-#+ EFlags +\r
-#+---------------------+\r
-#+ CS +\r
-#+---------------------+\r
-#+ EIP +\r
-#+---------------------+\r
-#+ Error Code +\r
-#+---------------------+\r
-#+ Vector Number +\r
-#+---------------------+\r
-#+ EBP +\r
-#+---------------------+ <-- EBP\r
-#\r
-# RSP set to odd multiple of 8 means ErrCode PRESENT\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(PageFaultIdtHandlerSmmProfile)\r
-ASM_PFX(PageFaultIdtHandlerSmmProfile):\r
- pushl $0x0e # Page Fault\r
- pushl %ebp\r
- movl %esp, %ebp\r
-\r
-\r
- #\r
- # Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32\r
- # is 16-byte aligned\r
- #\r
- andl $0xfffffff0, %esp\r
- subl $12, %esp\r
-\r
-## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- pushl %eax\r
- pushl %ecx\r
- pushl %edx\r
- pushl %ebx\r
- leal (6*4)(%ebp), %ecx\r
- pushl %ecx # ESP\r
- pushl (%ebp) # EBP\r
- pushl %esi\r
- pushl %edi\r
-\r
-## UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
- movl %ss, %eax\r
- pushl %eax\r
- movzwl (4*4)(%ebp), %eax\r
- pushl %eax\r
- movl %ds, %eax\r
- pushl %eax\r
- movl %es, %eax\r
- pushl %eax\r
- movl %fs, %eax\r
- pushl %eax\r
- movl %gs, %eax\r
- pushl %eax\r
-\r
-## UINT32 Eip;\r
- movl (3*4)(%ebp), %eax\r
- pushl %eax\r
-\r
-## UINT32 Gdtr[2], Idtr[2];\r
- subl $8, %esp\r
- sidt (%esp)\r
- movl 2(%esp), %eax\r
- xchgl (%esp), %eax\r
- andl $0xffff, %eax\r
- movl %eax, 4(%esp)\r
-\r
- subl $8, %esp\r
- sgdt (%esp)\r
- movl 2(%esp), %eax\r
- xchgl (%esp), %eax\r
- andl $0xffff, %eax\r
- movl %eax, 4(%esp)\r
-\r
-## UINT32 Ldtr, Tr;\r
- xorl %eax, %eax\r
- strw %ax\r
- pushl %eax\r
- sldtw %ax\r
- pushl %eax\r
-\r
-## UINT32 EFlags;\r
- movl (5*4)(%ebp), %eax\r
- pushl %eax\r
-\r
-## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- movl %cr4, %eax\r
- orl $0x208, %eax\r
- movl %eax, %cr4\r
- pushl %eax\r
- movl %cr3, %eax\r
- pushl %eax\r
- movl %cr2, %eax\r
- pushl %eax\r
- xorl %eax, %eax\r
- pushl %eax\r
- movl %cr0, %eax\r
- pushl %eax\r
-\r
-## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- movl %dr7, %eax\r
- pushl %eax\r
- movl %dr6, %eax\r
- pushl %eax\r
- movl %dr3, %eax\r
- pushl %eax\r
- movl %dr2, %eax\r
- pushl %eax\r
- movl %dr1, %eax\r
- pushl %eax\r
- movl %dr0, %eax\r
- pushl %eax\r
-\r
-## FX_SAVE_STATE_IA32 FxSaveState;\r
- subl $512, %esp\r
- movl %esp, %edi\r
- .byte 0x0f, 0xae, 0x07 #fxsave [edi]\r
-\r
-# UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
- cld\r
-\r
-## UINT32 ExceptionData;\r
- pushl (2*4)(%ebp)\r
-\r
-## call into exception handler\r
-\r
-## Prepare parameter and call\r
- movl %esp, %edx\r
- pushl %edx\r
- movl (1*4)(%ebp), %edx\r
- pushl %edx\r
-\r
- #\r
- # Call External Exception Handler\r
- #\r
- movl $ASM_PFX(SmiPFHandler), %eax\r
- call *%eax\r
- addl $8, %esp\r
- jmp L4\r
-\r
-L4:\r
-## UINT32 ExceptionData;\r
- addl $4, %esp\r
-\r
-## FX_SAVE_STATE_IA32 FxSaveState;\r
- movl %esp, %esi\r
- .byte 0xf, 0xae, 0xe # fxrstor [esi]\r
- addl $512, %esp\r
-\r
-## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
-## Skip restoration of DRx registers to support debuggers\r
-## that set breakpoints in interrupt/exception context\r
- addl $4*6, %esp\r
-\r
-## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- popl %eax\r
- movl %eax, %cr0\r
- addl $4, %esp # not for Cr1\r
- popl %eax\r
- movl %eax, %cr2\r
- popl %eax\r
- movl %eax, %cr3\r
- popl %eax\r
- movl %eax, %cr4\r
-\r
-## UINT32 EFlags;\r
- popl (5*4)(%ebp)\r
-\r
-## UINT32 Ldtr, Tr;\r
-## UINT32 Gdtr[2], Idtr[2];\r
-## Best not let anyone mess with these particular registers...\r
- addl $24, %esp\r
-\r
-## UINT32 Eip;\r
- popl (3*4)(%ebp)\r
-\r
-## UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
-## NOTE - modified segment registers could hang the debugger... We\r
-## could attempt to insulate ourselves against this possibility,\r
-## but that poses risks as well.\r
-##\r
- popl %gs\r
- popl %fs\r
- popl %es\r
- popl %ds\r
- popl (4*4)(%ebp)\r
- popl %ss\r
-\r
-## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- popl %edi\r
- popl %esi\r
- addl $4, %esp # not for ebp\r
- addl $4, %esp # not for esp\r
- popl %ebx\r
- popl %edx\r
- popl %ecx\r
- popl %eax\r
-\r
- movl %ebp, %esp\r
- popl %ebp\r
-\r
-# Enable TF bit after page fault handler runs\r
- btsl $8, 16(%esp) # EFLAGS\r
-\r
- addl $8, %esp # skip INT# & ErrCode\r
-Return:\r
- iret\r
-#\r
-# Page Fault Exception Handler entry when SMM Stack Guard is enabled\r
-# Executiot starts here after a task switch\r
-#\r
-PFHandlerEntry:\r
-#\r
-# Get this processor's TSS\r
-#\r
- subl $8, %esp\r
- sgdt 2(%esp)\r
- movl 4(%esp), %eax # GDT base\r
- addl $8, %esp\r
- movl (TSS_SEL+2)(%eax), %ecx\r
- shll $8, %ecx\r
- movb (TSS_SEL+7)(%eax), %cl\r
- rorl $8, %ecx # ecx = TSS base\r
-\r
- movl %esp, %ebp\r
-\r
- #\r
- # Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32\r
- # is 16-byte aligned\r
- #\r
- andl $0xfffffff0, %esp\r
- subl $12, %esp\r
-\r
-## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- pushl TSS_EAX(%ecx)\r
- pushl TSS_ECX(%ecx)\r
- pushl TSS_EDX(%ecx)\r
- pushl TSS_EBX(%ecx)\r
- pushl TSS_ESP(%ecx)\r
- pushl TSS_EBP(%ecx)\r
- pushl TSS_ESI(%ecx)\r
- pushl TSS_EDI(%ecx)\r
-\r
-## UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
- movzwl TSS_SS(%ecx), %eax\r
- pushl %eax\r
- movzwl TSS_CS(%ecx), %eax\r
- pushl %eax\r
- movzwl TSS_DS(%ecx), %eax\r
- pushl %eax\r
- movzwl TSS_ES(%ecx), %eax\r
- pushl %eax\r
- movzwl TSS_FS(%ecx), %eax\r
- pushl %eax\r
- movzwl TSS_GS(%ecx), %eax\r
- pushl %eax\r
-\r
-## UINT32 Eip;\r
- pushl TSS_EIP(%ecx)\r
-\r
-## UINT32 Gdtr[2], Idtr[2];\r
- subl $8, %esp\r
- sidt (%esp)\r
- movl 2(%esp), %eax\r
- xchgl (%esp), %eax\r
- andl $0xFFFF, %eax\r
- movl %eax, 4(%esp)\r
-\r
- subl $8, %esp\r
- sgdt (%esp)\r
- movl 2(%esp), %eax\r
- xchgl (%esp), %eax\r
- andl $0xFFFF, %eax\r
- movl %eax, 4(%esp)\r
-\r
-## UINT32 Ldtr, Tr;\r
- movl $TSS_SEL, %eax\r
- pushl %eax\r
- movzwl TSS_LDT(%ecx), %eax\r
- pushl %eax\r
-\r
-## UINT32 EFlags;\r
- pushl TSS_EFLAGS(%ecx)\r
-\r
-## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- movl %cr4, %eax\r
- orl $0x208, %eax\r
- movl %eax, %cr4\r
- pushl %eax\r
- movl %cr3, %eax\r
- pushl %eax\r
- movl %cr2, %eax\r
- pushl %eax\r
- xorl %eax, %eax\r
- pushl %eax\r
- movl %cr0, %eax\r
- pushl %eax\r
-\r
-## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- movl %dr7, %eax\r
- pushl %eax\r
- movl %dr6, %eax\r
- pushl %eax\r
- movl %dr3, %eax\r
- pushl %eax\r
- movl %dr2, %eax\r
- pushl %eax\r
- movl %dr1, %eax\r
- pushl %eax\r
- movl %dr0, %eax\r
- pushl %eax\r
-\r
-## FX_SAVE_STATE_IA32 FxSaveState;\r
-## Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)\r
-## when executing fxsave/fxrstor instruction\r
- clts\r
- subl $512, %esp\r
- movl %esp, %edi\r
- .byte 0x0f, 0xae, 0x07 #fxsave [edi]\r
-\r
-# UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
- cld\r
-\r
-## UINT32 ExceptionData;\r
- pushl (%ebp)\r
-\r
-## call into exception handler\r
- movl %ecx, %ebx\r
- movl $ASM_PFX(SmiPFHandler), %eax\r
-\r
-## Prepare parameter and call\r
- movl %esp, %edx\r
- pushl %edx\r
- movl $14, %edx\r
- pushl %edx\r
-\r
- #\r
- # Call External Exception Handler\r
- #\r
- call *%eax\r
- addl $8, %esp\r
-\r
- movl %ebx, %ecx\r
-## UINT32 ExceptionData;\r
- addl $4, %esp\r
-\r
-## FX_SAVE_STATE_IA32 FxSaveState;\r
- movl %esp, %esi\r
- .byte 0xf, 0xae, 0xe # fxrstor [esi]\r
- addl $512, %esp\r
-\r
-## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
-## Skip restoration of DRx registers to support debuggers\r
-## that set breakpoints in interrupt/exception context\r
- addl $4*6, %esp\r
-\r
-## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- popl %eax\r
- movl %eax, %cr0\r
- addl $4, %esp # not for Cr1\r
- popl %eax\r
- movl %eax, %cr2\r
- popl %eax\r
- movl %eax, TSS_CR3(%ecx)\r
- popl %eax\r
- movl %eax, %cr4\r
-\r
-## UINT32 EFlags;\r
- popl TSS_EFLAGS(%ecx)\r
-\r
-## UINT32 Ldtr, Tr;\r
-## UINT32 Gdtr[2], Idtr[2];\r
-## Best not let anyone mess with these particular registers...\r
- addl $24, %esp\r
-\r
-## UINT32 Eip;\r
- popl TSS_EIP(%ecx)\r
-\r
-## UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
-## NOTE - modified segment registers could hang the debugger... We\r
-## could attempt to insulate ourselves against this possibility,\r
-## but that poses risks as well.\r
-##\r
- popl %eax\r
- movw %ax, TSS_GS(%ecx)\r
- popl %eax\r
- movw %ax, TSS_FS(%ecx)\r
- popl %eax\r
- movw %ax, TSS_ES(%ecx)\r
- popl %eax\r
- movw %ax, TSS_DS(%ecx)\r
- popl %eax\r
- movw %ax, TSS_CS(%ecx)\r
- popl %eax\r
- movw %ax, TSS_SS(%ecx)\r
-\r
-## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- popl TSS_EDI(%ecx)\r
- popl TSS_ESI(%ecx)\r
- addl $4, %esp # not for ebp\r
- addl $4, %esp # not for esp\r
- popl TSS_EBX(%ecx)\r
- popl TSS_EDX(%ecx)\r
- popl TSS_ECX(%ecx)\r
- popl TSS_EAX(%ecx)\r
-\r
- movl %ebp, %esp\r
-\r
-# Set single step DB# if SMM profile is enabled and page fault exception happens\r
- cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))\r
- jz Done2\r
-# Create return context for iret in stub function\r
- movl TSS_ESP(%ecx), %eax # Get old stack pointer\r
- movl TSS_EIP(%ecx), %ebx\r
- movl %ebx, -0xc(%eax) # create EIP in old stack\r
- movzwl TSS_CS(%ecx), %ebx\r
- movl %ebx, -0x8(%eax) # create CS in old stack\r
- movl TSS_EFLAGS(%ecx), %ebx\r
- btsl $8,%ebx\r
- movl %ebx, -0x4(%eax) # create eflags in old stack\r
- movl TSS_ESP(%ecx), %eax # Get old stack pointer\r
- subl $12, %eax # minus 12 byte\r
- movl %eax, TSS_ESP(%ecx) # Set new stack pointer\r
-\r
-# Replace the EIP of interrupted task with stub function\r
- movl $ASM_PFX(PageFaultStubFunction), %eax\r
- movl %eax, TSS_EIP(%ecx)\r
-# Jump to the iret so next page fault handler as a task will start again after iret.\r
-\r
-Done2:\r
-\r
- addl $4, %esp # skip ErrCode\r
-\r
- jmp Return\r
-\r
-ASM_PFX(PageFaultStubFunction):\r
-#\r
-# we need clean TS bit in CR0 to execute\r
-# x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.\r
-#\r
- clts\r
- iret\r
projects / mirror_edk2.git / blobdiff