UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiException.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm
index f9f3986ea1cc6416be641d38070d69327be5bc93..e7b85a9949826712acef087b546c0c0e8666913f 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm
@@ -1,12 +1,6 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution.  The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+; Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
 ;\r
@@ -19,11 +13,12 @@
 ;-------------------------------------------------------------------------------\r
 \r
 extern  ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))\r
-extern  ASM_PFX(gSmiMtrrs)\r
 extern  ASM_PFX(SmiPFHandler)\r
+extern  ASM_PFX(mSetupDebugTrap)\r
 \r
 global  ASM_PFX(gcSmiIdtr)\r
 global  ASM_PFX(gcSmiGdtr)\r
+global  ASM_PFX(gTaskGateDescriptor)\r
 global  ASM_PFX(gcPsd)\r
 \r
     SECTION .data\r
@@ -88,7 +83,7 @@ TssSeg:
             DB      0x80                ; LimitHigh\r
             DB      0                   ; BaseHigh\r
 ExceptionTssSeg:\r
-            DW      TSS_DESC_SIZE       ; LimitLow\r
+            DW      EXCEPTION_TSS_DESC_SIZE       ; LimitLow\r
             DW      0                   ; BaseLow\r
             DB      0                   ; BaseMid\r
             DB      0x89\r
@@ -222,6 +217,8 @@ ExceptionTssDescriptor:
             DW      0                   ; Reserved\r
             DW      0                   ; T\r
             DW      0                   ; I/O Map Base\r
+            DD      0                   ; SSP\r
+EXCEPTION_TSS_DESC_SIZE equ $ - ExceptionTssDescriptor\r
 \r
 ASM_PFX(gcPsd):\r
             DB      'PSDSIG  '\r
@@ -242,7 +239,7 @@ ASM_PFX(gcPsd):
             DD      0\r
             times   24 DB 0\r
             DD      0\r
-            DD      ASM_PFX(gSmiMtrrs)\r
+            DD      0\r
 PSD_SIZE  equ $ - ASM_PFX(gcPsd)\r
 \r
 ASM_PFX(gcSmiGdtr):\r
@@ -250,21 +247,10 @@ ASM_PFX(gcSmiGdtr):
     DD      NullSeg\r
 \r
 ASM_PFX(gcSmiIdtr):\r
-    DW      IDT_SIZE - 1\r
-    DD      _SmiIDT\r
-\r
-_SmiIDT:\r
-%rep 32\r
-    DW      0                           ; Offset 0:15\r
-    DW      CODE_SEL                    ; Segment selector\r
-    DB      0                           ; Unused\r
-    DB      0x8e                         ; Interrupt Gate, Present\r
-    DW      0                           ; Offset 16:31\r
-%endrep\r
-\r
-IDT_SIZE equ $ - _SmiIDT\r
+    DW      0\r
+    DD      0\r
 \r
-TaskGateDescriptor:\r
+ASM_PFX(gTaskGateDescriptor):\r
     DW      0                           ; Reserved\r
     DW      EXCEPTION_TSS_SEL           ; TSS Segment selector\r
     DB      0                           ; Reserved\r
@@ -393,7 +379,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 ;; FX_SAVE_STATE_IA32 FxSaveState;\r
     sub     esp, 512\r
     mov     edi, esp\r
-    db      0xf, 0xae, 0x7 ;fxsave [edi]\r
+    fxsave  [edi]\r
 \r
 ; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
     cld\r
@@ -421,7 +407,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 \r
 ;; FX_SAVE_STATE_IA32 FxSaveState;\r
     mov     esi, esp\r
-    db      0xf, 0xae, 0xe ; fxrstor [esi]\r
+    fxrstor [esi]\r
     add     esp, 512\r
 \r
 ;; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
@@ -593,7 +579,7 @@ PFHandlerEntry:
     clts\r
     sub     esp, 512\r
     mov     edi, esp\r
-    db      0xf, 0xae, 0x7 ;fxsave [edi]\r
+    fxsave  [edi]\r
 \r
 ; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
     cld\r
@@ -623,7 +609,7 @@ PFHandlerEntry:
 \r
 ;; FX_SAVE_STATE_IA32 FxSaveState;\r
     mov     esi, esp\r
-    db      0xf, 0xae, 0xe ; fxrstor [esi]\r
+    fxrstor [esi]\r
     add     esp, 512\r
 \r
 ;; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
@@ -684,7 +670,7 @@ o16 mov     [ecx + IA32_TSS._SS], ax
     mov     esp, ebp\r
 \r
 ; Set single step DB# if SMM profile is enabled and page fault exception happens\r
-    cmp     byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))], 0\r
+    cmp     byte [dword ASM_PFX(mSetupDebugTrap)], 0\r
     jz      @Done2\r
 \r
 ; Create return context for iretd in stub function\r
@@ -717,21 +703,3 @@ ASM_PFX(PageFaultStubFunction):
     clts\r
     iretd\r
 \r
-global ASM_PFX(InitializeIDTSmmStackGuard)\r
-ASM_PFX(InitializeIDTSmmStackGuard):\r
-    push    ebx\r
-;\r
-; If SMM Stack Guard feature is enabled, the Page Fault Exception entry in IDT\r
-; is a Task Gate Descriptor so that when a Page Fault Exception occurrs,\r
-; the processors can use a known good stack in case stack is ran out.\r
-;\r
-    lea     ebx, [_SmiIDT + 14 * 8]\r
-    lea     edx, [TaskGateDescriptor]\r
-    mov     eax, [edx]\r
-    mov     [ebx], eax\r
-    mov     eax, [edx + 4]\r
-    mov     [ebx + 4], eax\r
-    pop     ebx\r
-    ret\r
-\r
-    END\r