UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index e96dd8d2392aea0d321100d455c829a8c98b182b..5ff3cd2e731fb142fc2d1a5a5fdb13ef405c3e9c 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -22,11 +22,10 @@ extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)\r
 extern ASM_PFX(mSmmRelocationOriginalAddress)\r
 \r
-global ASM_PFX(gSmmCr3)\r
-global ASM_PFX(gSmmCr4)\r
-global ASM_PFX(gSmmCr0)\r
-global ASM_PFX(gSmmJmpAddr)\r
-global ASM_PFX(gSmmInitStack)\r
+global ASM_PFX(gPatchSmmCr3)\r
+global ASM_PFX(gPatchSmmCr4)\r
+global ASM_PFX(gPatchSmmCr0)\r
+global ASM_PFX(gPatchSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gcSmmInitSize)\r
 global ASM_PFX(gcSmmInitTemplate)\r
@@ -41,45 +40,40 @@ ASM_PFX(gcSmiInitGdtr):
             DQ      0\r
 \r
 global ASM_PFX(SmmStartup)\r
+\r
+BITS 16\r
 ASM_PFX(SmmStartup):\r
-    DB      0x66\r
     mov     eax, 0x80000001             ; read capability\r
     cpuid\r
-    DB      0x66\r
     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
-    DB      0x66, 0xb8\r
-ASM_PFX(gSmmCr3): DD 0\r
+    and     ebx, BIT20                  ; extract NX capability bit\r
+    shr     ebx, 9                      ; shift bit to IA32_EFER.NXE[BIT11] position\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr3):\r
     mov     cr3, eax\r
-    DB      0x67, 0x66\r
-    lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
-    DB      0x66, 0xb8\r
-ASM_PFX(gSmmCr4): DD 0\r
+o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr4):\r
     mov     cr4, eax\r
-    DB      0x66\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
     rdmsr\r
-    DB      0x66\r
-    test    ebx, BIT20                  ; check NXE capability\r
-    jz      .1\r
-    or      ah, BIT3                    ; set NXE bit\r
+    or      eax, ebx                    ; set NXE bit if NX is available\r
     wrmsr\r
-.1:\r
-    DB      0x66, 0xb8\r
-ASM_PFX(gSmmCr0): DD 0\r
-    DB      0xbf, PROTECT_MODE_DS, 0    ; mov di, PROTECT_MODE_DS\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr0):\r
+    mov     di, PROTECT_MODE_DS\r
     mov     cr0, eax\r
-    DB      0x66, 0xea                   ; jmp far [ptr48]\r
-ASM_PFX(gSmmJmpAddr):\r
-    DD      @32bit\r
-    DW      PROTECT_MODE_CS\r
+    jmp     PROTECT_MODE_CS : dword @32bit\r
+\r
+BITS 32\r
 @32bit:\r
     mov     ds, edi\r
     mov     es, edi\r
     mov     fs, edi\r
     mov     gs, edi\r
     mov     ss, edi\r
-    DB      0xbc                        ; mov esp, imm32\r
-ASM_PFX(gSmmInitStack): DD 0\r
+    mov     esp, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmInitStack):\r
     call    ASM_PFX(SmmInitHandler)\r
     rsm\r
 \r