UefiCpuPkg/PiSmmCpuDxeSmm: Add EFIAPI to CheckFeatureSupported()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / MpService.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 83f5bf962d575c21cf7dce53ecbaa19f135c1bfd..79b7c90a809be8eb72e54c269a640e0397fda154 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -732,12 +732,14 @@ APHandler (
   Create 4G PageTable in SMRAM.\r
 \r
   @param          ExtraPages       Additional page numbers besides for 4G memory\r
+  @param          Is32BitPageTable Whether the page table is 32-bit PAE\r
   @return         PageTable Address\r
 \r
 **/\r
 UINT32\r
 Gen4GPageTable (\r
-  IN      UINTN                     ExtraPages\r
+  IN      UINTN                     ExtraPages,\r
+  IN      BOOLEAN                   Is32BitPageTable\r
   )\r
 {\r
   VOID    *PageTable;\r
@@ -770,7 +772,7 @@ Gen4GPageTable (
   //\r
   // Allocate the page table\r
   //\r
-  PageTable = AllocatePages (ExtraPages + 5 + PagesNeeded);\r
+  PageTable = AllocatePageTableMemory (ExtraPages + 5 + PagesNeeded);\r
   ASSERT (PageTable != NULL);\r
 \r
   PageTable = (VOID *)((UINTN)PageTable + EFI_PAGES_TO_SIZE (ExtraPages));\r
@@ -785,7 +787,7 @@ Gen4GPageTable (
   // Set Page Directory Pointers\r
   //\r
   for (Index = 0; Index < 4; Index++) {\r
-    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + IA32_PG_P;\r
+    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);\r
   }\r
   Pte += EFI_PAGE_SIZE / sizeof (*Pte);\r
 \r
@@ -793,7 +795,7 @@ Gen4GPageTable (
   // Fill in Page Directory Entries\r
   //\r
   for (Index = 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) {\r
-    Pte[Index] = (Index << 21) + IA32_PG_PS + IA32_PG_RW + IA32_PG_P;\r
+    Pte[Index] = (Index << 21) | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;\r
   }\r
 \r
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
@@ -802,7 +804,7 @@ Gen4GPageTable (
     Pdpte = (UINT64*)PageTable;\r
     for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {\r
       Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~(EFI_PAGE_SIZE - 1));\r
-      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages + IA32_PG_RW + IA32_PG_P;\r
+      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | PAGE_ATTRIBUTE_BITS;\r
       //\r
       // Fill in Page Table Entries\r
       //\r
@@ -819,7 +821,7 @@ Gen4GPageTable (
             GuardPage = 0;\r
           }\r
         } else {\r
-          Pte[Index] = PageAddress + IA32_PG_RW + IA32_PG_P;\r
+          Pte[Index] = PageAddress | PAGE_ATTRIBUTE_BITS;\r
         }\r
         PageAddress+= EFI_PAGE_SIZE;\r
       }\r
@@ -872,7 +874,7 @@ SetCacheability (
     //\r
     // Allocate a page from SMRAM\r
     //\r
-    NewPageTableAddress = AllocatePages (1);\r
+    NewPageTableAddress = AllocatePageTableMemory (1);\r
     ASSERT (NewPageTableAddress != NULL);\r
 \r
     NewPageTable = (UINT64 *)NewPageTableAddress;\r
@@ -886,7 +888,7 @@ SetCacheability (
       NewPageTable[Index] |= (UINT64)(Index << EFI_PAGE_SHIFT);\r
     }\r
 \r
-    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | IA32_PG_P;\r
+    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_ATTRIBUTE_BITS;\r
   }\r
 \r
   ASSERT (PageTable[PTIndex] & IA32_PG_P);\r
@@ -941,7 +943,7 @@ SmmStartupThisAp (
 }\r
 \r
 /**\r
-  This funciton sets DR6 & DR7 according to SMM save state, before running SMM C code.\r
+  This function sets DR6 & DR7 according to SMM save state, before running SMM C code.\r
   They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.\r
 \r
   NOTE: It might not be appreciated in runtime since it might\r
@@ -959,7 +961,7 @@ CpuSmmDebugEntry (
   SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
   \r
   if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
-    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
       AsmWriteDr6 (CpuSaveState->x86._DR6);\r
       AsmWriteDr7 (CpuSaveState->x86._DR7);\r
@@ -971,7 +973,7 @@ CpuSmmDebugEntry (
 }\r
 \r
 /**\r
-  This funciton restores DR6 & DR7 to SMM save state.\r
+  This function restores DR6 & DR7 to SMM save state.\r
 \r
   NOTE: It might not be appreciated in runtime since it might\r
         conflict with OS debugging facilities. Turn them off in RELEASE.\r
@@ -988,7 +990,7 @@ CpuSmmDebugExit (
   SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
 \r
   if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
-    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
       CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();\r
       CpuSaveState->x86._DR6 = (UINT32)AsmReadDr6 ();\r