Move SmmDebug feature from ASM to C.

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / MpService.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 3e8b0936aa8415aa1f980a77ccbd399eaff6dd78..83f5bf962d575c21cf7dce53ecbaa19f135c1bfd 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -940,6 +940,65 @@ SmmStartupThisAp (
   return EFI_SUCCESS;\r
 }\r
 \r
+/**\r
+  This funciton sets DR6 & DR7 according to SMM save state, before running SMM C code.\r
+  They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.\r
+\r
+  NOTE: It might not be appreciated in runtime since it might\r
+        conflict with OS debugging facilities. Turn them off in RELEASE.\r
+\r
+  @param    CpuIndex              CPU Index\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSmmDebugEntry (\r
+  IN UINTN  CpuIndex\r
+  )\r
+{\r
+  SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
+  \r
+  if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
+    if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
+      AsmWriteDr6 (CpuSaveState->x86._DR6);\r
+      AsmWriteDr7 (CpuSaveState->x86._DR7);\r
+    } else {\r
+      AsmWriteDr6 ((UINTN)CpuSaveState->x64._DR6);\r
+      AsmWriteDr7 ((UINTN)CpuSaveState->x64._DR7);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  This funciton restores DR6 & DR7 to SMM save state.\r
+\r
+  NOTE: It might not be appreciated in runtime since it might\r
+        conflict with OS debugging facilities. Turn them off in RELEASE.\r
+\r
+  @param    CpuIndex              CPU Index\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSmmDebugExit (\r
+  IN UINTN  CpuIndex\r
+  )\r
+{\r
+  SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
+\r
+  if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
+    if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
+      CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();\r
+      CpuSaveState->x86._DR6 = (UINT32)AsmReadDr6 ();\r
+    } else {\r
+      CpuSaveState->x64._DR7 = AsmReadDr7 ();\r
+      CpuSaveState->x64._DR6 = AsmReadDr6 ();\r
+    }\r
+  }\r
+}\r
+\r
 /**\r
   C function for SMI entry, each processor comes here upon SMI trigger.\r
 \r