UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr0" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index a3fd796dba4a8d6a487f13138c133f22bda86dc6..f602d86d51a141252dc1651f0ea678b0a1606b22 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -128,6 +128,7 @@ UINT8                    mPhysicalAddressBits;
 //\r
 // Control register contents saved for SMM S3 resume state initialization.\r
 //\r
+UINT32                   mSmmCr0;\r
 UINT32                   mSmmCr4;\r
 \r
 /**\r
@@ -410,7 +411,8 @@ SmmRelocateBases (
   //\r
   // Patch ASM code template with current CR0, CR3, and CR4 values\r
   //\r
-  gSmmCr0 = (UINT32)AsmReadCr0 ();\r
+  mSmmCr0 = (UINT32)AsmReadCr0 ();\r
+  PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r
   PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
   mSmmCr4 = (UINT32)AsmReadCr4 ();\r
   PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r