UefiCpuPkg: Not touch SmmFeatureControl if Code_Access_Chk not Set

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index e210c8d44659357e02e6989021148e57842e287c..532ac0974b7de7d48e6f3c9d8dcb8b106d28404f 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -76,13 +76,6 @@ EFI_SMM_CPU_PROTOCOL  mSmmCpu  = {
 \r
 EFI_CPU_INTERRUPT_HANDLER   mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
 \r
-///\r
-/// SMM CPU Save State Protocol instance\r
-///\r
-EFI_SMM_CPU_SAVE_STATE_PROTOCOL  mSmmCpuSaveState = {\r
-  NULL\r
-};\r
-\r
 //\r
 // SMM stack information\r
 //\r
@@ -530,18 +523,13 @@ SmmRestoreCpu (
   }\r
 \r
   //\r
-  // Do below CPU things for native platform only\r
+  // Skip initialization if mAcpiCpuData is not valid\r
   //\r
-  if (!FeaturePcdGet(PcdFrameworkCompatibilitySupport)) {\r
+  if (mAcpiCpuData.NumberOfCpus > 0) {\r
     //\r
-    // Skip initialization if mAcpiCpuData is not valid\r
+    // First time microcode load and restore MTRRs\r
     //\r
-    if (mAcpiCpuData.NumberOfCpus > 0) {\r
-      //\r
-      // First time microcode load and restore MTRRs\r
-      //\r
-      EarlyInitializeCpu ();\r
-    }\r
+    EarlyInitializeCpu ();\r
   }\r
 \r
   //\r
@@ -550,18 +538,13 @@ SmmRestoreCpu (
   SmmRelocateBases ();\r
 \r
   //\r
-  // Do below CPU things for native platform only\r
+  // Skip initialization if mAcpiCpuData is not valid\r
   //\r
-  if (!FeaturePcdGet(PcdFrameworkCompatibilitySupport)) {\r
+  if (mAcpiCpuData.NumberOfCpus > 0) {\r
     //\r
-    // Skip initialization if mAcpiCpuData is not valid\r
+    // Restore MSRs for BSP and all APs\r
     //\r
-    if (mAcpiCpuData.NumberOfCpus > 0) {\r
-      //\r
-      // Restore MSRs for BSP and all APs\r
-      //\r
-      InitializeCpu ();\r
-    }\r
+    InitializeCpu ();\r
   }\r
 \r
   //\r
@@ -686,13 +669,6 @@ SmmReadyToLockEventNotify (
   //\r
   mAcpiCpuData.NumberOfCpus = 0;\r
 \r
-  //\r
-  // If FrameworkCompatibilitySspport is enabled, then do not copy CPU S3 Data into SMRAM\r
-  //\r
-  if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
-    goto Done;\r
-  }\r
-\r
   //\r
   // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM\r
   //\r
@@ -1009,7 +985,6 @@ PiCpuSmmEntry (
 \r
   mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;\r
   mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState     = gSmmCpuPrivate->CpuSaveState;\r
-  mSmmCpuSaveState.CpuSaveState = (EFI_SMM_CPU_STATE **)gSmmCpuPrivate->CpuSaveState;\r
 \r
   //\r
   // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.\r
@@ -1150,25 +1125,6 @@ PiCpuSmmEntry (
   Status = InitializeSmmCpuServices (mSmmCpuHandle);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
-    //\r
-    // Install Framework SMM Save State Protocol into UEFI protocol database for backward compatibility\r
-    //\r
-    Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (\r
-                                          &gSmmCpuPrivate->SmmCpuHandle,\r
-                                          &gEfiSmmCpuSaveStateProtocolGuid,\r
-                                          &mSmmCpuSaveState,\r
-                                          NULL\r
-                                          );\r
-    ASSERT_EFI_ERROR (Status);\r
-    //\r
-    // The SmmStartupThisAp service in Framework SMST should always be non-null.\r
-    // Update SmmStartupThisAp pointer in PI SMST here so that PI/Framework SMM thunk\r
-    // can have it ready when constructing Framework SMST.\r
-    //\r
-    gSmst->SmmStartupThisAp = SmmStartupThisAp;\r
-  }\r
-\r
   //\r
   // register SMM Ready To Lock Protocol notification\r
   //\r
@@ -1353,9 +1309,9 @@ ConfigSmmCodeAccessCheckOnCurrentProcessor (
   NewSmmFeatureControlMsr = SmmFeatureControlMsr;\r
   if (mSmmCodeAccessCheckEnable) {\r
     NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;\r
-  }\r
-  if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r
-    NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;\r
+    if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r
+      NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;\r
+    }\r
   }\r
 \r
   //\r
@@ -1386,7 +1342,7 @@ ConfigSmmCodeAccessCheck (
   //\r
   // Check to see if the Feature Control MSR is supported on this CPU\r
   //\r
-  Index = gSmst->CurrentlyExecutingCpu;\r
+  Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;\r
   if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {\r
     mSmmCodeAccessCheckEnable = FALSE;\r
     return;\r
@@ -1398,13 +1354,6 @@ ConfigSmmCodeAccessCheck (
   //\r
   if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {\r
     mSmmCodeAccessCheckEnable = FALSE;\r
-  }\r
-\r
-  //\r
-  // If the SMM Code Access Check feature is disabled and the Feature Control MSR\r
-  // is not being locked, then no additional work is required\r
-  //\r
-  if (!mSmmCodeAccessCheckEnable && !FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r
     return;\r
   }\r
 \r
@@ -1428,7 +1377,7 @@ ConfigSmmCodeAccessCheck (
   // Enable SMM Code Access Check feature for the APs.\r
   //\r
   for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
-    if (Index != gSmst->CurrentlyExecutingCpu) {\r
+    if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {\r
 \r
       //\r
       // Acquire Config SMM Code Access Check spin lock.  The AP will release the\r