MdePkg/BaseLib: add PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 2cb0bbcff65c7c5dfdf3aad7954e9ba0f36bb044..a27d1f4684f5cc0e0d2b601544cba445d5469714 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -1,7 +1,7 @@
 /** @file\r
 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
 \r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -76,6 +76,15 @@ EFI_SMM_CPU_PROTOCOL  mSmmCpu  = {
   SmmWriteSaveState\r
 };\r
 \r
+///\r
+/// SMM Memory Attribute Protocol instance\r
+///\r
+EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  mSmmMemoryAttribute  = {\r
+  EdkiiSmmGetMemoryAttributes,\r
+  EdkiiSmmSetMemoryAttributes,\r
+  EdkiiSmmClearMemoryAttributes\r
+};\r
+\r
 EFI_CPU_INTERRUPT_HANDLER   mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
 \r
 //\r
@@ -114,6 +123,8 @@ SPIN_LOCK                *mConfigSmmCodeAccessCheckLock = NULL;
 EFI_SMRAM_DESCRIPTOR     *mSmmCpuSmramRanges;\r
 UINTN                    mSmmCpuSmramRangeCount;\r
 \r
+UINT8                    mPhysicalAddressBits;\r
+\r
 /**\r
   Initialize IDT to setup exception handlers for SMM.\r
 \r
@@ -178,7 +189,7 @@ DumpModuleInfoByIp (
   //\r
   // Find Image Base\r
   //\r
-  Pe32Data = PeCoffSerachImageBase (CallerIpAddress);\r
+  Pe32Data = PeCoffSearchImageBase (CallerIpAddress);\r
   if (Pe32Data != 0) {\r
     DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));\r
     PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);\r
@@ -531,6 +542,12 @@ PiCpuSmmEntry (
   UINTN                      ModelId;\r
   UINT32                     Cr3;\r
 \r
+  //\r
+  // Initialize address fixup\r
+  //\r
+  PiSmmCpuSmmInitFixupAddress ();\r
+  PiSmmCpuSmiEntryFixupAddress ();\r
+\r
   //\r
   // Initialize Debug Agent to support source level debug in SMM code\r
   //\r
@@ -891,6 +908,17 @@ PiCpuSmmEntry (
                     );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
+  //\r
+  // Install the SMM Memory Attribute Protocol into SMM protocol database\r
+  //\r
+  Status = gSmst->SmmInstallProtocolInterface (\r
+                    &mSmmCpuHandle,\r
+                    &gEdkiiSmmMemoryAttributeProtocolGuid,\r
+                    EFI_NATIVE_INTERFACE,\r
+                    &mSmmMemoryAttribute\r
+                    );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
   //\r
   // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.\r
   //\r
@@ -1117,7 +1145,12 @@ ConfigSmmCodeAccessCheck (
   //\r
   for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
     if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {\r
-\r
+      if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r
+        //\r
+        // If this processor does not exist\r
+        //\r
+        continue;\r
+      }\r
       //\r
       // Acquire Config SMM Code Access Check spin lock.  The AP will release the\r
       // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r