\r
UINT8 mPhysicalAddressBits;\r
\r
+//\r
+// Control register contents saved for SMM S3 resume state initialization.\r
+//\r
+UINT32 mSmmCr0;\r
+UINT32 mSmmCr4;\r
+\r
/**\r
Initialize IDT to setup exception handlers for SMM.\r
\r
//\r
// Patch ASM code template with current CR0, CR3, and CR4 values\r
//\r
- gSmmCr0 = (UINT32)AsmReadCr0 ();\r
- gSmmCr3 = (UINT32)AsmReadCr3 ();\r
- gSmmCr4 = (UINT32)AsmReadCr4 ();\r
+ mSmmCr0 = (UINT32)AsmReadCr0 ();\r
+ PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r
+ PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
+ mSmmCr4 = (UINT32)AsmReadCr4 ();\r
+ PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r
\r
//\r
// Patch GDTR for SMM base relocation\r