UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI.

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 71af2f17759560c3a4a24bcfb628bf669864e8d2..1cf85c1481a76e547331d06e2681e02e45365786 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1,7 +1,7 @@
 /** @file\r
 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
 \r
-Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -105,6 +105,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
 \r
+#define SMRR_MAX_ADDRESS       BASE_4GB\r
+\r
 typedef enum {\r
   PageNone,\r
   Page4K,\r
@@ -415,6 +417,9 @@ extern UINTN                               mSemaphoreSize;
 extern SPIN_LOCK                           *mPFLock;\r
 extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;\r
 extern SPIN_LOCK                           *mMemoryMappedLock;\r
+extern EFI_SMRAM_DESCRIPTOR                *mSmmCpuSmramRanges;\r
+extern UINTN                               mSmmCpuSmramRangeCount;\r
+extern UINT8                               mPhysicalAddressBits;\r
 \r
 //\r
 // Copy of the PcdPteMemoryEncryptionAddressOrMask\r
@@ -690,8 +695,8 @@ SmmRelocateBases (
 VOID\r
 EFIAPI\r
 SmiPFHandler (\r
-    IN EFI_EXCEPTION_TYPE   InterruptType,\r
-    IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE   InterruptType,\r
+  IN EFI_SYSTEM_CONTEXT   SystemContext\r
   );\r
 \r
 /**\r