/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <CpuHotPlugData.h>\r
\r
#include <Register/Cpuid.h>\r
+#include <Register/Msr.h>\r
\r
#include "CpuService.h"\r
#include "SmmProfile.h"\r
///\r
#define IA32_PG_P BIT0\r
#define IA32_PG_RW BIT1\r
+#define IA32_PG_U BIT2\r
#define IA32_PG_WT BIT3\r
#define IA32_PG_CD BIT4\r
#define IA32_PG_A BIT5\r
+#define IA32_PG_D BIT6\r
#define IA32_PG_PS BIT7\r
#define IA32_PG_PAT_2M BIT12\r
#define IA32_PG_PAT_4K IA32_PG_PS\r
#define IA32_PG_PMNT BIT62\r
#define IA32_PG_NX BIT63\r
\r
+#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)\r
+//\r
+// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
+// X64 PAE PDPTE does not have such restriction\r
+//\r
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
+\r
//\r
// Size of Task-State Segment defined in IA32 Manual\r
//\r
extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
extern UINTN mMaxNumberOfCpus;\r
extern UINTN mNumberOfCpus;\r
-extern BOOLEAN mRestoreSmmConfigurationInS3;\r
extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
\r
///\r
/// The type of SMM CPU Information\r
///\r
typedef struct {\r
- SPIN_LOCK Busy;\r
+ SPIN_LOCK *Busy;\r
volatile EFI_AP_PROCEDURE Procedure;\r
volatile VOID *Parameter;\r
- volatile UINT32 Run;\r
- volatile BOOLEAN Present;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
} SMM_CPU_DATA_BLOCK;\r
\r
typedef enum {\r
// so that UC cache-ability can be set together.\r
//\r
SMM_CPU_DATA_BLOCK *CpuData;\r
- volatile UINT32 Counter;\r
+ volatile UINT32 *Counter;\r
volatile UINT32 BspIndex;\r
- volatile BOOLEAN InsideSmm;\r
- volatile BOOLEAN AllCpusInSync;\r
+ volatile BOOLEAN *InsideSmm;\r
+ volatile BOOLEAN *AllCpusInSync;\r
volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
volatile BOOLEAN SwitchBsp;\r
volatile BOOLEAN *CandidateBsp;\r
} SMM_DISPATCHER_MP_SYNC_DATA;\r
\r
+#define MSR_SPIN_LOCK_INIT_NUM 15\r
+\r
typedef struct {\r
- SPIN_LOCK SpinLock;\r
+ SPIN_LOCK *SpinLock;\r
UINT32 MsrIndex;\r
} MP_MSR_LOCK;\r
\r
UINT64 MtrrBaseMaskPtr; // Offset 0x58\r
} PROCESSOR_SMM_DESCRIPTOR;\r
\r
+\r
+///\r
+/// All global semaphores' pointer\r
+///\r
+typedef struct {\r
+ volatile UINT32 *Counter;\r
+ volatile BOOLEAN *InsideSmm;\r
+ volatile BOOLEAN *AllCpusInSync;\r
+ SPIN_LOCK *PFLock;\r
+ SPIN_LOCK *CodeAccessCheckLock;\r
+ SPIN_LOCK *MemoryMappedLock;\r
+} SMM_CPU_SEMAPHORE_GLOBAL;\r
+\r
+///\r
+/// All semaphores for each processor\r
+///\r
+typedef struct {\r
+ SPIN_LOCK *Busy;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
+} SMM_CPU_SEMAPHORE_CPU;\r
+\r
+///\r
+/// All MSRs semaphores' pointer and counter\r
+///\r
+typedef struct {\r
+ SPIN_LOCK *Msr;\r
+ UINTN AvailableCounter;\r
+} SMM_CPU_SEMAPHORE_MSR;\r
+\r
+///\r
+/// All semaphores' information\r
+///\r
+typedef struct {\r
+ SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
+ SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
+ SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r
+} SMM_CPU_SEMAPHORES;\r
+\r
extern IA32_DESCRIPTOR gcSmiGdtr;\r
extern IA32_DESCRIPTOR gcSmiIdtr;\r
extern VOID *gcSmiIdtrPtr;\r
extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r
extern UINT64 gPhyMask;\r
-extern ACPI_CPU_DATA mAcpiCpuData;\r
extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
-extern VOID *mGdtForAp;\r
-extern VOID *mIdtForAp;\r
-extern VOID *mMachineCheckHandlerForAp;\r
extern UINTN mSmmStackArrayBase;\r
extern UINTN mSmmStackArrayEnd;\r
extern UINTN mSmmStackSize;\r
extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
+extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
+extern UINTN mSemaphoreSize;\r
+extern SPIN_LOCK *mPFLock;\r
+extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
+extern SPIN_LOCK *mMemoryMappedLock;\r
\r
/**\r
Create 4G PageTable in SMRAM.\r
\r
@param ExtraPages Additional page numbers besides for 4G memory\r
+ @param Is32BitPageTable Whether the page table is 32-bit PAE\r
@return PageTable Address\r
\r
**/\r
UINT32\r
Gen4GPageTable (\r
- IN UINTN ExtraPages\r
+ IN UINTN ExtraPages,\r
+ IN BOOLEAN Is32BitPageTable\r
);\r
\r
\r
);\r
\r
/**\r
- The function is invoked before SMBASE relocation in S3 path to restores CPU status.\r
+ Relocate SmmBases for each processor.\r
\r
- The function is invoked before SMBASE relocation in S3 path. It does first time microcode load\r
- and restores MTRRs for both BSP and APs.\r
+ Execute on first boot and all S3 resumes\r
\r
**/\r
VOID\r
-EarlyInitializeCpu (\r
- VOID\r
- );\r
-\r
-/**\r
- The function is invoked after SMBASE relocation in S3 path to restores CPU status.\r
-\r
- The function is invoked after SMBASE relocation in S3 path. It restores configuration according to\r
- data saved by normal boot path for both BSP and APs.\r
-\r
-**/\r
-VOID\r
-InitializeCpu (\r
+EFIAPI\r
+SmmRelocateBases (\r
VOID\r
);\r
\r
VOID\r
);\r
\r
+/**\r
+ Perform the pre tasks.\r
+\r
+**/\r
+VOID\r
+PerformPreTasks (\r
+ VOID\r
+ );\r
+\r
/**\r
Initialize MSR spin lock by MSR index.\r
\r
DumpModuleInfoByIp (\r
IN UINTN CallerIpAddress\r
);\r
+\r
+/**\r
+ This API provides a way to allocate memory for page table.\r
+\r
+ This API can be called more once to allocate memory for page tables.\r
+\r
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
+ returned.\r
+\r
+ @param Pages The number of 4 KB pages to allocate.\r
+\r
+ @return A pointer to the allocated buffer or NULL if allocation fails.\r
+\r
+**/\r
+VOID *\r
+AllocatePageTableMemory (\r
+ IN UINTN Pages\r
+ );\r
+\r
+\r
+//\r
+// S3 related global variable and function prototype.\r
+//\r
+\r
+extern BOOLEAN mSmmS3Flag;\r
+\r
+/**\r
+ Initialize SMM S3 resume state structure used during S3 Resume.\r
+\r
+ @param[in] Cr3 The base address of the page tables to use in SMM.\r
+\r
+**/\r
+VOID\r
+InitSmmS3ResumeState (\r
+ IN UINT32 Cr3\r
+ );\r
+\r
+/**\r
+ Get ACPI CPU data.\r
+\r
+**/\r
+VOID\r
+GetAcpiCpuData (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Restore SMM Configuration in S3 boot path.\r
+\r
+**/\r
+VOID\r
+RestoreSmmConfigurationInS3 (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Get ACPI S3 enable flag.\r
+\r
+**/\r
+VOID\r
+GetAcpiS3EnableFlag (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r
+\r
+ @param[in] ApHltLoopCode The 32-bit address of the safe hlt-loop function.\r
+ @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r
+\r
+**/\r
+VOID\r
+TransferApToSafeState (\r
+ IN UINT32 ApHltLoopCode,\r
+ IN UINT32 TopOfStack\r
+ );\r
+\r
#endif\r
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