/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <CpuHotPlugData.h>\r
\r
#include <Register/Cpuid.h>\r
+#include <Register/Msr.h>\r
\r
#include "CpuService.h"\r
#include "SmmProfile.h"\r
/// The type of SMM CPU Information\r
///\r
typedef struct {\r
- SPIN_LOCK Busy;\r
+ SPIN_LOCK *Busy;\r
volatile EFI_AP_PROCEDURE Procedure;\r
volatile VOID *Parameter;\r
- volatile UINT32 Run;\r
- volatile BOOLEAN Present;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
} SMM_CPU_DATA_BLOCK;\r
\r
typedef enum {\r
// so that UC cache-ability can be set together.\r
//\r
SMM_CPU_DATA_BLOCK *CpuData;\r
- volatile UINT32 Counter;\r
+ volatile UINT32 *Counter;\r
volatile UINT32 BspIndex;\r
- volatile BOOLEAN InsideSmm;\r
- volatile BOOLEAN AllCpusInSync;\r
+ volatile BOOLEAN *InsideSmm;\r
+ volatile BOOLEAN *AllCpusInSync;\r
volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
volatile BOOLEAN SwitchBsp;\r
volatile BOOLEAN *CandidateBsp;\r
} SMM_DISPATCHER_MP_SYNC_DATA;\r
\r
+#define MSR_SPIN_LOCK_INIT_NUM 15\r
+\r
typedef struct {\r
- SPIN_LOCK SpinLock;\r
+ SPIN_LOCK *SpinLock;\r
UINT32 MsrIndex;\r
} MP_MSR_LOCK;\r
\r
UINT64 MtrrBaseMaskPtr; // Offset 0x58\r
} PROCESSOR_SMM_DESCRIPTOR;\r
\r
+\r
+///\r
+/// All global semaphores' pointer\r
+///\r
+typedef struct {\r
+ volatile UINT32 *Counter;\r
+ volatile BOOLEAN *InsideSmm;\r
+ volatile BOOLEAN *AllCpusInSync;\r
+ SPIN_LOCK *PFLock;\r
+ SPIN_LOCK *CodeAccessCheckLock;\r
+} SMM_CPU_SEMAPHORE_GLOBAL;\r
+\r
+///\r
+/// All semaphores for each processor\r
+///\r
+typedef struct {\r
+ SPIN_LOCK *Busy;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
+} SMM_CPU_SEMAPHORE_CPU;\r
+\r
+///\r
+/// All MSRs semaphores' pointer and counter\r
+///\r
+typedef struct {\r
+ SPIN_LOCK *Msr;\r
+ UINTN AvailableCounter;\r
+} SMM_CPU_SEMAPHORE_MSR;\r
+\r
+///\r
+/// All semaphores' information\r
+///\r
+typedef struct {\r
+ SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
+ SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
+ SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r
+} SMM_CPU_SEMAPHORES;\r
+\r
extern IA32_DESCRIPTOR gcSmiGdtr;\r
extern IA32_DESCRIPTOR gcSmiIdtr;\r
extern VOID *gcSmiIdtrPtr;\r
extern UINTN mSmmStackSize;\r
extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
+extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
+extern UINTN mSemaphoreSize;\r
+extern SPIN_LOCK *mPFLock;\r
+extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
\r
/**\r
Create 4G PageTable in SMRAM.\r