UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned buffer

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index f2a91655a33b85bdbf3c69b30252d172c877fe98..eca42aa8d69863b93b114fcc0852afa078bfec7b 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1,7 +1,7 @@
 /** @file\r
 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
 \r
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -53,6 +53,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <CpuHotPlugData.h>\r
 \r
 #include <Register/Cpuid.h>\r
+#include <Register/Msr.h>\r
 \r
 #include "CpuService.h"\r
 #include "SmmProfile.h"\r
@@ -71,15 +72,24 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///\r
 #define IA32_PG_P                   BIT0\r
 #define IA32_PG_RW                  BIT1\r
+#define IA32_PG_U                   BIT2\r
 #define IA32_PG_WT                  BIT3\r
 #define IA32_PG_CD                  BIT4\r
 #define IA32_PG_A                   BIT5\r
+#define IA32_PG_D                   BIT6\r
 #define IA32_PG_PS                  BIT7\r
 #define IA32_PG_PAT_2M              BIT12\r
 #define IA32_PG_PAT_4K              IA32_PG_PS\r
 #define IA32_PG_PMNT                BIT62\r
 #define IA32_PG_NX                  BIT63\r
 \r
+#define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)\r
+//\r
+// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
+// X64 PAE PDPTE does not have such restriction\r
+//\r
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)\r
+\r
 //\r
 // Size of Task-State Segment defined in IA32 Manual\r
 //\r
@@ -304,10 +314,10 @@ typedef struct {
   // so that UC cache-ability can be set together.\r
   //\r
   SMM_CPU_DATA_BLOCK            *CpuData;\r
-  volatile UINT32               Counter;\r
+  volatile UINT32               *Counter;\r
   volatile UINT32               BspIndex;\r
-  volatile BOOLEAN              InsideSmm;\r
-  volatile BOOLEAN              AllCpusInSync;\r
+  volatile BOOLEAN              *InsideSmm;\r
+  volatile BOOLEAN              *AllCpusInSync;\r
   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;\r
   volatile BOOLEAN              SwitchBsp;\r
   volatile BOOLEAN              *CandidateBsp;\r
@@ -344,6 +354,25 @@ typedef struct {
   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58\r
 } PROCESSOR_SMM_DESCRIPTOR;\r
 \r
+\r
+///\r
+/// All global semaphores' pointer\r
+///\r
+typedef struct {\r
+  volatile UINT32      *Counter;\r
+  volatile BOOLEAN     *InsideSmm;\r
+  volatile BOOLEAN     *AllCpusInSync;\r
+  SPIN_LOCK            *PFLock;\r
+  SPIN_LOCK            *CodeAccessCheckLock;\r
+} SMM_CPU_SEMAPHORE_GLOBAL;\r
+\r
+///\r
+/// All semaphores' information\r
+///\r
+typedef struct {\r
+  SMM_CPU_SEMAPHORE_GLOBAL          SemaphoreGlobal;\r
+} SMM_CPU_SEMAPHORES;\r
+\r
 extern IA32_DESCRIPTOR                     gcSmiGdtr;\r
 extern IA32_DESCRIPTOR                     gcSmiIdtr;\r
 extern VOID                                *gcSmiIdtrPtr;\r
@@ -359,17 +388,21 @@ extern UINTN                               mSmmStackArrayEnd;
 extern UINTN                               mSmmStackSize;\r
 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;\r
 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;\r
+extern SPIN_LOCK                           *mPFLock;\r
+extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;\r
 \r
 /**\r
   Create 4G PageTable in SMRAM.\r
 \r
   @param          ExtraPages       Additional page numbers besides for 4G memory\r
+  @param          Is32BitPageTable Whether the page table is 32-bit PAE\r
   @return         PageTable Address\r
 \r
 **/\r
 UINT32\r
 Gen4GPageTable (\r
-  IN      UINTN                     ExtraPages\r
+  IN      UINTN                     ExtraPages,\r
+  IN      BOOLEAN                   Is32BitPageTable\r
   );\r
 \r
 \r