UefiCpuPkg/PiSmm: Fix various typos

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / SmmCpuMemoryManagement.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 48f5f954cbc9b03beed8a9661f6090ab74cc1438..9c5a92af6479d54e913bdd285cef01eb15875b45 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -1,13 +1,7 @@
 /** @file\r
 \r
 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -131,18 +125,36 @@ GetPageTableEntry (
   UINTN                 Index2;\r
   UINTN                 Index3;\r
   UINTN                 Index4;\r
+  UINTN                 Index5;\r
   UINT64                *L1PageTable;\r
   UINT64                *L2PageTable;\r
   UINT64                *L3PageTable;\r
   UINT64                *L4PageTable;\r
+  UINT64                *L5PageTable;\r
+  IA32_CR4              Cr4;\r
+  BOOLEAN               Enable5LevelPaging;\r
 \r
+  Index5 = ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK;\r
   Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK;\r
   Index3 = ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK;\r
   Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;\r
   Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;\r
 \r
+  Cr4.UintN = AsmReadCr4 ();\r
+  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
+\r
   if (sizeof(UINTN) == sizeof(UINT64)) {\r
-    L4PageTable = (UINT64 *)GetPageTableBase ();\r
+    if (Enable5LevelPaging) {\r
+      L5PageTable = (UINT64 *)GetPageTableBase ();\r
+      if (L5PageTable[Index5] == 0) {\r
+        *PageAttribute = PageNone;\r
+        return NULL;\r
+      }\r
+\r
+      L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
+    } else {\r
+      L4PageTable = (UINT64 *)GetPageTableBase ();\r
+    }\r
     if (L4PageTable[Index4] == 0) {\r
       *PageAttribute = PageNone;\r
       return NULL;\r
@@ -453,7 +465,7 @@ ConvertMemoryPageAttributes (
   }\r
 \r
   //\r
-  // Below logic is to check 2M/4K page to make sure we donot waist memory.\r
+  // Below logic is to check 2M/4K page to make sure we do not waste memory.\r
   //\r
   while (Length != 0) {\r
     PageEntry = GetPageTableEntry (BaseAddress, &PageAttribute);\r
@@ -1053,7 +1065,7 @@ IsUefiPageNotPresent (
 }\r
 \r
 /**\r
-  Merge continous memory map entries whose type is\r
+  Merge continuous memory map entries whose type is\r
   EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory,\r
   EfiUnusableMemory, EfiACPIReclaimMemory, because the memory described by\r
   these entries will be set as NOT present in SMM page table.\r