UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / SmmProfile.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 91b8e7ddb991d1948e66d903cfe21aea7896637f..3abc87c97777d5277135b76925bb8c5031638cfe 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -1,7 +1,7 @@
 /** @file\r
 Enable SMM profile.\r
 \r
-Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -927,7 +927,7 @@ InitSmmProfileInternal (
 }\r
 \r
 /**\r
-  Check if XD feature is supported by a processor.\r
+  Check if feature is supported by a processor.\r
 \r
 **/\r
 VOID\r
@@ -936,9 +936,23 @@ CheckFeatureSupported (
   )\r
 {\r
   UINT32                         RegEax;\r
+  UINT32                         RegEcx;\r
   UINT32                         RegEdx;\r
   MSR_IA32_MISC_ENABLE_REGISTER  MiscEnableMsr;\r
 \r
+  if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
+    AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
+    if (RegEax <= CPUID_EXTENDED_FUNCTION) {\r
+      mCetSupported = FALSE;\r
+      PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r
+    }\r
+    AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, NULL);\r
+    if ((RegEcx & CPUID_CET_SS) == 0) {\r
+      mCetSupported = FALSE;\r
+      PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r
+    }\r
+  }\r
+\r
   if (mXdSupported) {\r
     AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
     if (RegEax <= CPUID_EXTENDED_FUNCTION) {\r