UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Remove unnecessary BTS MSRs

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / SmmProfile.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index ff4e28ec58e43572fcb0057e24d859ed102d0628..8ecc5415a341fe90b9a49b2dab10805283a5763d 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -1,7 +1,7 @@
 /** @file\r
 Enable SMM profile.\r
 \r
-Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -342,7 +342,6 @@ InitProtectedMemRange (
   UINTN                            NumberOfSpliteRange;\r
   EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *MemorySpaceMap;\r
   UINTN                            TotalSize;\r
-  EFI_STATUS                       Status;\r
   EFI_PHYSICAL_ADDRESS             ProtectBaseAddress;\r
   EFI_PHYSICAL_ADDRESS             ProtectEndAddress;\r
   EFI_PHYSICAL_ADDRESS             Top2MBAlignedAddress;\r
@@ -358,10 +357,10 @@ InitProtectedMemRange (
   //\r
   // Get MMIO ranges from GCD and add them into protected memory ranges.\r
   //\r
-  Status = gDS->GetMemorySpaceMap (\r
-                &NumberOfDescriptors,\r
-                &MemorySpaceMap\r
-                );\r
+  gDS->GetMemorySpaceMap (\r
+       &NumberOfDescriptors,\r
+       &MemorySpaceMap\r
+       );\r
   for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {\r
       NumberOfMmioDescriptors++;\r
@@ -557,9 +556,9 @@ InitPaging (
 \r
           // Split it\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {\r
-            Pt[Level4] = Address + ((Level4 << 12) | IA32_PG_RW | IA32_PG_P);\r
+            Pt[Level4] = Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS);\r
           } // end for PT\r
-          *Pte = (UINTN)Pt | IA32_PG_RW | IA32_PG_P;\r
+          *Pte = (UINTN)Pt | PAGE_ATTRIBUTE_BITS;\r
         } // end if IsAddressSplit\r
       } // end for PTE\r
     } // end for PDE\r
@@ -608,7 +607,7 @@ InitPaging (
             //\r
             // Patch to remove Present flag and RW flag\r
             //\r
-            *Pte = *Pte & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+            *Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
           }\r
           if (Nx && mXdSupported) {\r
             *Pte = *Pte | IA32_PG_NX;\r
@@ -621,7 +620,7 @@ InitPaging (
           }\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {\r
             if (!IsAddressValid (Address, &Nx)) {\r
-              *Pt = *Pt & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+              *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
             }\r
             if (Nx && mXdSupported) {\r
               *Pt = *Pt | IA32_PG_NX;\r
@@ -776,18 +775,16 @@ InitSmmProfileCallBack (
   IN EFI_HANDLE      Handle\r
   )\r
 {\r
-  EFI_STATUS         Status;\r
-\r
   //\r
   // Save to variable so that SMM profile data can be found.\r
   //\r
-  Status = gRT->SetVariable (\r
-                  SMM_PROFILE_NAME,\r
-                  &gEfiCallerIdGuid,\r
-                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
-                  sizeof(mSmmProfileBase),\r
-                  &mSmmProfileBase\r
-                  );\r
+  gRT->SetVariable (\r
+         SMM_PROFILE_NAME,\r
+         &gEfiCallerIdGuid,\r
+         EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
+         sizeof(mSmmProfileBase),\r
+         &mSmmProfileBase\r
+         );\r
 \r
   //\r
   // Get Software SMI from FADT\r
@@ -928,10 +925,13 @@ InitSmmProfileInternal (
 /**\r
   Check if XD feature is supported by a processor.\r
 \r
+  @param[in,out] Buffer  The pointer to private data buffer.\r
+\r
 **/\r
 VOID\r
+EFIAPI\r
 CheckFeatureSupported (\r
-  VOID\r
+  IN OUT VOID   *Buffer\r
   )\r
 {\r
   UINT32                 RegEax;\r
@@ -966,10 +966,9 @@ CheckFeatureSupported (
       //    BTINT bits in the MSR_DEBUGCTLA MSR.\r
       // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.\r
       //\r
-      if ((AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 11, 11) == 0) &&\r
-          (AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 12, 12) == 0)) {\r
+      if (AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 11, 11) == 1) {\r
         //\r
-        // BTS facilities is supported.\r
+        // BTS facilities is not supported if MSR_IA32_MISC_ENABLE BIT11 is set.\r
         //\r
         mBtsSupported = FALSE;\r
       }\r
@@ -1001,7 +1000,7 @@ CheckProcessorFeature (
   //\r
   // Check if XD and BTS are supported on all processors.\r
   //\r
-  CheckFeatureSupported ();\r
+  CheckFeatureSupported (NULL);\r
 \r
   //\r
   //Check on other processors if BSP supports this\r
@@ -1009,7 +1008,7 @@ CheckProcessorFeature (
   if (mXdSupported || mBtsSupported) {\r
     MpServices->StartupAllAPs (\r
                   MpServices,\r
-                  (EFI_AP_PROCEDURE) CheckFeatureSupported,\r
+                  CheckFeatureSupported,\r
                   TRUE,\r
                   NULL,\r
                   0,\r
@@ -1072,8 +1071,6 @@ ActivateLBR (
   if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {\r
     return ;\r
   }\r
-  AsmWriteMsr64 (MSR_LER_FROM_LIP, 0);\r
-  AsmWriteMsr64 (MSR_LER_TO_LIP, 0);\r
   DebugCtl |= MSR_DEBUG_CTL_LBR;\r
   AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);\r
 }\r
@@ -1244,7 +1241,7 @@ RestorePageTableBelow4G (
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));\r
     PageTable[PTIndex] |= (UINT64)IA32_PG_PS;\r
-    PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+    PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r
@@ -1277,7 +1274,7 @@ RestorePageTableBelow4G (
     // Set new entry\r
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));\r
-    PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+    PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r
@@ -1308,7 +1305,6 @@ SmmProfilePFHandler (
   SMM_PROFILE_ENTRY     *SmmProfileEntry;\r
   UINT64                SmiCommand;\r
   EFI_STATUS            Status;\r
-  UINTN                 SwSmiCpuIndex;\r
   UINT8                 SoftSmiValue;\r
   EFI_SMM_SAVE_STATE_IO_INFO    IoInfo;\r
 \r
@@ -1351,10 +1347,6 @@ SmmProfilePFHandler (
       }\r
     }\r
 \r
-    //\r
-    // Try to find which CPU trigger SWSMI\r
-    //\r
-    SwSmiCpuIndex = 0;\r
     //\r
     // Indicate it is not software SMI\r
     //\r
@@ -1365,10 +1357,6 @@ SmmProfilePFHandler (
         continue;\r
       }\r
       if (IoInfo.IoPort == mSmiCommandPort) {\r
-        //\r
-        // Great! Find it.\r
-        //\r
-        SwSmiCpuIndex = Index;\r
         //\r
         // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.\r
         //\r