UefiCpuPkg: Add PiSmmCpuDxeSmm module no IA32/X64 files

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / SmmProfileInternal.h

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
new file mode 100644 (file)
index 0000000..de6eb0a
--- /dev/null
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
@@ -0,0 +1,172 @@
+/** @file\r
+SMM profile internal header file.\r
+\r
+Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SMM_PROFILE_INTERNAL_H_\r
+#define _SMM_PROFILE_INTERNAL_H_\r
+\r
+#include <Guid/GlobalVariable.h>\r
+#include <Guid/Acpi.h>\r
+#include <Protocol/SmmReadyToLock.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/CpuLib.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+#include "SmmProfileArch.h"\r
+\r
+//\r
+// Configure the SMM_PROFILE DTS region size\r
+//\r
+#define SMM_PROFILE_DTS_SIZE       (4 * 1024 * 1024) // 4M\r
+\r
+#define MAX_PF_PAGE_COUNT           0x2\r
+\r
+#define PEBS_RECORD_NUMBER          0x2\r
+\r
+#define MAX_PF_ENTRY_COUNT          10\r
+\r
+//\r
+// This MACRO just enable unit test for the profile\r
+// Please disable it.\r
+//\r
+\r
+#define IA32_PF_EC_P                (1u << 0)\r
+#define IA32_PF_EC_WR               (1u << 1)\r
+#define IA32_PF_EC_US               (1u << 2)\r
+#define IA32_PF_EC_RSVD             (1u << 3)\r
+#define IA32_PF_EC_ID               (1u << 4)\r
+\r
+#define SMM_PROFILE_NAME            L"SmmProfileData"\r
+\r
+//\r
+// CPU generic definition\r
+//\r
+#define   CPUID1_EDX_XD_SUPPORT      0x100000\r
+#define   MSR_EFER                   0xc0000080\r
+#define   MSR_EFER_XD                0x800\r
+\r
+#define   CPUID1_EDX_BTS_AVAILABLE   0x200000\r
+\r
+#define   DR6_SINGLE_STEP            0x4000\r
+#define   RFLAG_TF                   0x100\r
+\r
+#define MSR_DEBUG_CTL                0x1D9\r
+#define   MSR_DEBUG_CTL_LBR          0x1\r
+#define   MSR_DEBUG_CTL_TR           0x40\r
+#define   MSR_DEBUG_CTL_BTS          0x80\r
+#define   MSR_DEBUG_CTL_BTINT        0x100\r
+#define MSR_LASTBRANCH_TOS           0x1C9\r
+#define MSR_LER_FROM_LIP             0x1DD\r
+#define MSR_LER_TO_LIP               0x1DE\r
+#define MSR_DS_AREA                  0x600\r
+\r
+typedef struct {\r
+  EFI_PHYSICAL_ADDRESS   Base;\r
+  EFI_PHYSICAL_ADDRESS   Top;\r
+} MEMORY_RANGE;\r
+\r
+typedef struct {\r
+  MEMORY_RANGE   Range;\r
+  BOOLEAN        Present;\r
+  BOOLEAN        Nx;\r
+} MEMORY_PROTECTION_RANGE;\r
+\r
+typedef struct {\r
+  UINT64  HeaderSize;\r
+  UINT64  MaxDataEntries;\r
+  UINT64  MaxDataSize;\r
+  UINT64  CurDataEntries;\r
+  UINT64  CurDataSize;\r
+  UINT64  TsegStart;\r
+  UINT64  TsegSize;\r
+  UINT64  NumSmis;\r
+  UINT64  NumCpus;\r
+} SMM_PROFILE_HEADER;\r
+\r
+typedef struct {\r
+  UINT64  SmiNum;\r
+  UINT64  CpuNum;\r
+  UINT64  ApicId;\r
+  UINT64  ErrorCode;\r
+  UINT64  Instruction;\r
+  UINT64  Address;\r
+  UINT64  SmiCmd;\r
+} SMM_PROFILE_ENTRY;\r
+\r
+extern SMM_S3_RESUME_STATE       *mSmmS3ResumeState;\r
+extern UINTN                     gSmiExceptionHandlers[];\r
+extern BOOLEAN                   mXdSupported;\r
+extern UINTN                     *mPFEntryCount;\r
+extern UINT64                    (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
+extern UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r
+\r
+//\r
+// Internal functions\r
+//\r
+\r
+/**\r
+  Update IDT table to replace page fault handler and INT 1 handler.\r
+\r
+**/\r
+VOID\r
+InitIdtr (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Check if the memory address will be mapped by 4KB-page.\r
+\r
+  @param  Address  The address of Memory.\r
+\r
+**/\r
+BOOLEAN\r
+IsAddressSplit (\r
+  IN EFI_PHYSICAL_ADDRESS   Address\r
+  );\r
+\r
+/**\r
+  Check if the memory address will be mapped by 4KB-page.\r
+\r
+  @param  Address  The address of Memory.\r
+  @param  Nx       The flag indicates if the memory is execute-disable.\r
+\r
+**/\r
+BOOLEAN\r
+IsAddressValid (\r
+  IN EFI_PHYSICAL_ADDRESS   Address,\r
+  IN BOOLEAN                *Nx\r
+  );\r
+\r
+/**\r
+  Page Fault handler for SMM use.\r
+\r
+**/\r
+VOID\r
+SmiDefaultPFHandler (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Clear TF in FLAGS.\r
+\r
+  @param  SystemContext    A pointer to the processor context when\r
+                           the interrupt occurred on the processor.\r
+\r
+**/\r
+VOID\r
+ClearTrapFlag (\r
+  IN OUT EFI_SYSTEM_CONTEXT   SystemContext\r
+  );\r
+\r
+#endif // _SMM_PROFILE_H_\r