/** @file\r
SMM profile internal header file.\r
\r
-Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _SMM_PROFILE_INTERNAL_H_\r
#define _SMM_PROFILE_INTERNAL_H_\r
\r
-#include <Guid/GlobalVariable.h>\r
-#include <Guid/Acpi.h>\r
#include <Protocol/SmmReadyToLock.h>\r
#include <Library/UefiRuntimeServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/CpuLib.h>\r
+#include <Library/UefiCpuLib.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
#include "SmmProfileArch.h"\r
//\r
// Configure the SMM_PROFILE DTS region size\r
//\r
-#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M\r
+#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M\r
\r
-#define MAX_PF_PAGE_COUNT 0x2\r
+#define MAX_PF_PAGE_COUNT 0x2\r
\r
-#define PEBS_RECORD_NUMBER 0x2\r
+#define PEBS_RECORD_NUMBER 0x2\r
\r
-#define MAX_PF_ENTRY_COUNT 10\r
+#define MAX_PF_ENTRY_COUNT 10\r
\r
//\r
// This MACRO just enable unit test for the profile\r
// Please disable it.\r
//\r
\r
-#define IA32_PF_EC_ID (1u << 4)\r
+#define IA32_PF_EC_ID (1u << 4)\r
\r
-#define SMM_PROFILE_NAME L"SmmProfileData"\r
+#define SMM_PROFILE_NAME L"SmmProfileData"\r
\r
//\r
// CPU generic definition\r
//\r
-#define CPUID1_EDX_XD_SUPPORT 0x100000\r
-#define MSR_EFER 0xc0000080\r
-#define MSR_EFER_XD 0x800\r
+#define CPUID1_EDX_XD_SUPPORT 0x100000\r
+#define MSR_EFER 0xc0000080\r
+#define MSR_EFER_XD 0x800\r
+\r
+#define CPUID1_EDX_BTS_AVAILABLE 0x200000\r
+\r
+#define DR6_SINGLE_STEP 0x4000\r
+#define RFLAG_TF 0x100\r
\r
-#define CPUID1_EDX_BTS_AVAILABLE 0x200000\r
+#define MSR_DEBUG_CTL 0x1D9\r
+#define MSR_DEBUG_CTL_LBR 0x1\r
+#define MSR_DEBUG_CTL_TR 0x40\r
+#define MSR_DEBUG_CTL_BTS 0x80\r
+#define MSR_DEBUG_CTL_BTINT 0x100\r
+#define MSR_DS_AREA 0x600\r
\r
-#define DR6_SINGLE_STEP 0x4000\r
-#define RFLAG_TF 0x100\r
+#define HEAP_GUARD_NONSTOP_MODE \\r
+ ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)\r
\r
-#define MSR_DEBUG_CTL 0x1D9\r
-#define MSR_DEBUG_CTL_LBR 0x1\r
-#define MSR_DEBUG_CTL_TR 0x40\r
-#define MSR_DEBUG_CTL_BTS 0x80\r
-#define MSR_DEBUG_CTL_BTINT 0x100\r
-#define MSR_DS_AREA 0x600\r
+#define NULL_DETECTION_NONSTOP_MODE \\r
+ ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)\r
\r
typedef struct {\r
- EFI_PHYSICAL_ADDRESS Base;\r
- EFI_PHYSICAL_ADDRESS Top;\r
+ EFI_PHYSICAL_ADDRESS Base;\r
+ EFI_PHYSICAL_ADDRESS Top;\r
} MEMORY_RANGE;\r
\r
typedef struct {\r
- MEMORY_RANGE Range;\r
- BOOLEAN Present;\r
- BOOLEAN Nx;\r
+ MEMORY_RANGE Range;\r
+ BOOLEAN Present;\r
+ BOOLEAN Nx;\r
} MEMORY_PROTECTION_RANGE;\r
\r
typedef struct {\r
- UINT64 HeaderSize;\r
- UINT64 MaxDataEntries;\r
- UINT64 MaxDataSize;\r
- UINT64 CurDataEntries;\r
- UINT64 CurDataSize;\r
- UINT64 TsegStart;\r
- UINT64 TsegSize;\r
- UINT64 NumSmis;\r
- UINT64 NumCpus;\r
+ UINT64 HeaderSize;\r
+ UINT64 MaxDataEntries;\r
+ UINT64 MaxDataSize;\r
+ UINT64 CurDataEntries;\r
+ UINT64 CurDataSize;\r
+ UINT64 TsegStart;\r
+ UINT64 TsegSize;\r
+ UINT64 NumSmis;\r
+ UINT64 NumCpus;\r
} SMM_PROFILE_HEADER;\r
\r
typedef struct {\r
- UINT64 SmiNum;\r
- UINT64 CpuNum;\r
- UINT64 ApicId;\r
- UINT64 ErrorCode;\r
- UINT64 Instruction;\r
- UINT64 Address;\r
- UINT64 SmiCmd;\r
+ UINT64 SmiNum;\r
+ UINT64 CpuNum;\r
+ UINT64 ApicId;\r
+ UINT64 ErrorCode;\r
+ UINT64 Instruction;\r
+ UINT64 Address;\r
+ UINT64 SmiCmd;\r
} SMM_PROFILE_ENTRY;\r
\r
-extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;\r
-extern UINTN gSmiExceptionHandlers[];\r
-extern BOOLEAN mXdSupported;\r
-extern UINTN *mPFEntryCount;\r
-extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
+extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;\r
+extern UINTN gSmiExceptionHandlers[];\r
+extern BOOLEAN mXdSupported;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;\r
+extern UINTN *mPFEntryCount;\r
+extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r
\r
//\r
**/\r
BOOLEAN\r
IsAddressSplit (\r
- IN EFI_PHYSICAL_ADDRESS Address\r
+ IN EFI_PHYSICAL_ADDRESS Address\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsAddressValid (\r
- IN EFI_PHYSICAL_ADDRESS Address,\r
- IN BOOLEAN *Nx\r
+ IN EFI_PHYSICAL_ADDRESS Address,\r
+ IN BOOLEAN *Nx\r
);\r
\r
/**\r
**/\r
VOID\r
ClearTrapFlag (\r
- IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
);\r
\r
#endif // _SMM_PROFILE_H_\r
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