UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmiEntry.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 741e4b7da2bd1061cd9b3bbae350aeeb22f24f48..271492a9d7220b13c8de2b329e2788a60da26ac3 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -69,6 +69,7 @@ extern ASM_PFX(mXdSupported)
 global ASM_PFX(gPatchXdSupported)\r
 global ASM_PFX(gPatchSmiStack)\r
 global ASM_PFX(gPatchSmiCr3)\r
+global ASM_PFX(gPatch5LevelPagingSupport)\r
 global ASM_PFX(gcSmiHandlerTemplate)\r
 global ASM_PFX(gcSmiHandlerSize)\r
 \r
@@ -124,6 +125,17 @@ ProtFlatMode:
 ASM_PFX(gPatchSmiCr3):\r
     mov     cr3, rax\r
     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3\r
+\r
+    mov     cl, strict byte 0            ; source operand will be patched\r
+ASM_PFX(gPatch5LevelPagingSupport):\r
+    cmp     cl, 0\r
+    je      SkipEnable5LevelPaging\r
+    ;\r
+    ; Enable 5-Level Paging bit\r
+    ;\r
+    bts     eax, 12                     ; Set LA57 bit (bit #12)\r
+SkipEnable5LevelPaging:\r
+\r
     mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.\r
 ; Load TSS\r
     sub     esp, 8                      ; reserve room in stack\r