UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmiEntry.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 271492a9d7220b13c8de2b329e2788a60da26ac3..db06d22d51f4804fc939dd6e55450a8f29170b9a 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -69,7 +69,7 @@ extern ASM_PFX(mXdSupported)
 global ASM_PFX(gPatchXdSupported)\r
 global ASM_PFX(gPatchSmiStack)\r
 global ASM_PFX(gPatchSmiCr3)\r
-global ASM_PFX(gPatch5LevelPagingSupport)\r
+global ASM_PFX(gPatch5LevelPagingNeeded)\r
 global ASM_PFX(gcSmiHandlerTemplate)\r
 global ASM_PFX(gcSmiHandlerSize)\r
 \r
@@ -127,7 +127,7 @@ ASM_PFX(gPatchSmiCr3):
     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3\r
 \r
     mov     cl, strict byte 0            ; source operand will be patched\r
-ASM_PFX(gPatch5LevelPagingSupport):\r
+ASM_PFX(gPatch5LevelPagingNeeded):\r
     cmp     cl, 0\r
     je      SkipEnable5LevelPaging\r
     ;\r