;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;\r
;\r
;-------------------------------------------------------------------------------\r
\r
-%include "StuffRsb.inc"\r
+%include "StuffRsbNasm.inc"\r
+%include "Nasm.inc"\r
\r
;\r
-; Variables referrenced by C code\r
+; Variables referenced by C code\r
;\r
\r
+%define MSR_IA32_S_CET 0x6A2\r
+%define MSR_IA32_CET_SH_STK_EN 0x1\r
+%define MSR_IA32_CET_WR_SHSTK_EN 0x2\r
+%define MSR_IA32_CET_ENDBR_EN 0x4\r
+%define MSR_IA32_CET_LEG_IW_EN 0x8\r
+%define MSR_IA32_CET_NO_TRACK_EN 0x10\r
+%define MSR_IA32_CET_SUPPRESS_DIS 0x20\r
+%define MSR_IA32_CET_SUPPRESS 0x400\r
+%define MSR_IA32_CET_TRACKER 0x800\r
+%define MSR_IA32_PL0_SSP 0x6A4\r
+%define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR 0x6A8\r
+\r
+%define CR4_CET 0x800000\r
+\r
%define MSR_IA32_MISC_ENABLE 0x1A0\r
%define MSR_EFER 0xc0000080\r
%define MSR_EFER_XD 0x800\r
global ASM_PFX(gPatchSmbase)\r
extern ASM_PFX(mXdSupported)\r
global ASM_PFX(gPatchXdSupported)\r
+global ASM_PFX(gPatchMsrIa32MiscEnableSupported)\r
global ASM_PFX(gPatchSmiStack)\r
global ASM_PFX(gPatchSmiCr3)\r
+global ASM_PFX(gPatch5LevelPagingNeeded)\r
global ASM_PFX(gcSmiHandlerTemplate)\r
global ASM_PFX(gcSmiHandlerSize)\r
\r
+extern ASM_PFX(mCetSupported)\r
+global ASM_PFX(mPatchCetSupported)\r
+global ASM_PFX(mPatchCetPl0Ssp)\r
+global ASM_PFX(mPatchCetInterruptSsp)\r
+global ASM_PFX(mPatchCetInterruptSspTable)\r
+\r
DEFAULT REL\r
SECTION .text\r
\r
ASM_PFX(gPatchSmiCr3):\r
mov cr3, rax\r
mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3\r
+\r
+ mov cl, strict byte 0 ; source operand will be patched\r
+ASM_PFX(gPatch5LevelPagingNeeded):\r
+ cmp cl, 0\r
+ je SkipEnable5LevelPaging\r
+ ;\r
+ ; Enable 5-Level Paging bit\r
+ ;\r
+ bts eax, 12 ; Set LA57 bit (bit #12)\r
+SkipEnable5LevelPaging:\r
+\r
mov cr4, rax ; in PreModifyMtrrs() to flush TLB.\r
; Load TSS\r
sub esp, 8 ; reserve room in stack\r
ASM_PFX(gPatchXdSupported):\r
cmp al, 0\r
jz @SkipXd\r
+\r
+; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit\r
+ mov al, strict byte 1 ; source operand may be patched\r
+ASM_PFX(gPatchMsrIa32MiscEnableSupported):\r
+ cmp al, 1\r
+ jz MsrIa32MiscEnableSupported\r
+\r
+; MSR_IA32_MISC_ENABLE not supported\r
+ sub esp, 4\r
+ xor rdx, rdx\r
+ push rdx ; don't try to restore the XD Disable bit just before RSM\r
+ jmp EnableNxe\r
+\r
;\r
; Check XD disable bit\r
;\r
+MsrIa32MiscEnableSupported:\r
mov ecx, MSR_IA32_MISC_ENABLE\r
rdmsr\r
sub esp, 4\r
push rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz .0\r
+ jz EnableNxe\r
and dx, 0xFFFB ; clear XD Disable bit if it is set\r
wrmsr\r
-.0:\r
+EnableNxe:\r
mov ecx, MSR_EFER\r
rdmsr\r
or ax, MSR_EFER_XD ; enable NXE\r
mov ax, [rbx + DSC_SS]\r
mov ss, eax\r
\r
-_SmiHandler:\r
- mov rbx, [rsp + 0x8] ; rcx <- CpuIndex\r
+ mov rbx, [rsp + 0x8] ; rbx <- CpuIndex\r
+\r
+; enable CET if supported\r
+ mov al, strict byte 1 ; source operand may be patched\r
+ASM_PFX(mPatchCetSupported):\r
+ cmp al, 0\r
+ jz CetDone\r
+\r
+ mov ecx, MSR_IA32_S_CET\r
+ rdmsr\r
+ push rdx\r
+ push rax\r
+\r
+ mov ecx, MSR_IA32_PL0_SSP\r
+ rdmsr\r
+ push rdx\r
+ push rax\r
+\r
+ mov ecx, MSR_IA32_INTERRUPT_SSP_TABLE_ADDR\r
+ rdmsr\r
+ push rdx\r
+ push rax\r
+\r
+ mov ecx, MSR_IA32_S_CET\r
+ mov eax, MSR_IA32_CET_SH_STK_EN\r
+ xor edx, edx\r
+ wrmsr\r
+\r
+ mov ecx, MSR_IA32_PL0_SSP\r
+ mov eax, strict dword 0 ; source operand will be patched\r
+ASM_PFX(mPatchCetPl0Ssp):\r
+ xor edx, edx\r
+ wrmsr\r
+ mov rcx, cr0\r
+ btr ecx, 16 ; clear WP\r
+ mov cr0, rcx\r
+ mov [eax], eax ; reload SSP, and clear busyflag.\r
+ xor ecx, ecx\r
+ mov [eax + 4], ecx\r
+\r
+ mov ecx, MSR_IA32_INTERRUPT_SSP_TABLE_ADDR\r
+ mov eax, strict dword 0 ; source operand will be patched\r
+ASM_PFX(mPatchCetInterruptSspTable):\r
+ xor edx, edx\r
+ wrmsr\r
+\r
+ mov eax, strict dword 0 ; source operand will be patched\r
+ASM_PFX(mPatchCetInterruptSsp):\r
+ cmp eax, 0\r
+ jz CetInterruptDone\r
+ mov [eax], eax ; reload SSP, and clear busyflag.\r
+ xor ecx, ecx\r
+ mov [eax + 4], ecx\r
+CetInterruptDone:\r
+\r
+ mov rcx, cr0\r
+ bts ecx, 16 ; set WP\r
+ mov cr0, rcx\r
+\r
+ mov eax, 0x668 | CR4_CET\r
+ mov cr4, rax\r
+\r
+ setssbsy\r
+\r
+CetDone:\r
\r
;\r
; Save FP registers\r
\r
add rsp, 0x200\r
\r
+ mov rax, strict qword 0 ; mov rax, ASM_PFX(mCetSupported)\r
+mCetSupportedAbsAddr:\r
+ mov al, [rax]\r
+ cmp al, 0\r
+ jz CetDone2\r
+\r
+ mov eax, 0x668\r
+ mov cr4, rax ; disable CET\r
+\r
+ mov ecx, MSR_IA32_INTERRUPT_SSP_TABLE_ADDR\r
+ pop rax\r
+ pop rdx\r
+ wrmsr\r
+\r
+ mov ecx, MSR_IA32_PL0_SSP\r
+ pop rax\r
+ pop rdx\r
+ wrmsr\r
+\r
+ mov ecx, MSR_IA32_S_CET\r
+ pop rax\r
+ pop rdx\r
+ wrmsr\r
+CetDone2:\r
+\r
mov rax, strict qword 0 ; lea rax, [ASM_PFX(mXdSupported)]\r
mXdSupportedAbsAddr:\r
mov al, [rax]\r
wrmsr\r
\r
.1:\r
+\r
StuffRsb64\r
rsm\r
\r
lea rax, [ASM_PFX(mXdSupported)]\r
lea rcx, [mXdSupportedAbsAddr]\r
mov qword [rcx - 8], rax\r
+\r
+ lea rax, [ASM_PFX(mCetSupported)]\r
+ lea rcx, [mCetSupportedAbsAddr]\r
+ mov qword [rcx - 8], rax\r
ret\r
projects / mirror_edk2.git / blobdiff