+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SmiException.asm\r
-;\r
-; Abstract:\r
-;\r
-; Exception handlers used in SM mode\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-EXTERNDEF SmiPFHandler:PROC\r
-EXTERNDEF gcSmiIdtr:FWORD\r
-EXTERNDEF gcSmiGdtr:FWORD\r
-EXTERNDEF gcPsd:BYTE\r
-\r
- .const\r
-\r
-NullSeg DQ 0 ; reserved by architecture\r
-CodeSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 9bh\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-ProtModeCodeSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 9bh\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-ProtModeSsSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 93h\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-DataSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 93h\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-CodeSeg16 LABEL QWORD\r
- DW -1\r
- DW 0\r
- DB 0\r
- DB 9bh\r
- DB 8fh\r
- DB 0\r
-DataSeg16 LABEL QWORD\r
- DW -1\r
- DW 0\r
- DB 0\r
- DB 93h\r
- DB 8fh\r
- DB 0\r
-CodeSeg64 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 9bh\r
- DB 0afh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-; TSS Segment for X64 specially\r
-TssSeg LABEL QWORD\r
- DW TSS_DESC_SIZE - 1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 89h\r
- DB 00h ; LimitHigh\r
- DB 0 ; BaseHigh\r
- DD 0 ; BaseUpper\r
- DD 0 ; Reserved\r
-GDT_SIZE = $ - offset NullSeg\r
-\r
-; Create TSS Descriptor just after GDT\r
-TssDescriptor LABEL BYTE\r
- DD 0 ; Reserved\r
- DQ 0 ; RSP0\r
- DQ 0 ; RSP1\r
- DQ 0 ; RSP2\r
- DD 0 ; Reserved\r
- DD 0 ; Reserved\r
- DQ 0 ; IST1\r
- DQ 0 ; IST2\r
- DQ 0 ; IST3\r
- DQ 0 ; IST4\r
- DQ 0 ; IST5\r
- DQ 0 ; IST6\r
- DQ 0 ; IST7\r
- DD 0 ; Reserved\r
- DD 0 ; Reserved\r
- DW 0 ; Reserved\r
- DW 0 ; I/O Map Base Address\r
-TSS_DESC_SIZE = $ - offset TssDescriptor\r
-\r
-;\r
-; This structure serves as a template for all processors.\r
-;\r
-gcPsd LABEL BYTE\r
- DB 'PSDSIG '\r
- DW PSD_SIZE\r
- DW 2\r
- DW 1 SHL 2\r
- DW CODE_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW 0\r
- DQ 0\r
- DQ 0\r
- DQ 0 ; fixed in InitializeMpServiceData()\r
- DQ offset NullSeg\r
- DD GDT_SIZE\r
- DD 0\r
- DB 24 dup (0)\r
- DQ 0\r
-PSD_SIZE = $ - offset gcPsd\r
-\r
-;\r
-; CODE & DATA segments for SMM runtime\r
-;\r
-CODE_SEL = offset CodeSeg64 - offset NullSeg\r
-DATA_SEL = offset DataSeg32 - offset NullSeg\r
-CODE32_SEL = offset CodeSeg32 - offset NullSeg\r
-\r
-gcSmiGdtr LABEL FWORD\r
- DW GDT_SIZE - 1\r
- DQ offset NullSeg\r
-\r
-gcSmiIdtr LABEL FWORD\r
- DW 0\r
- DQ 0\r
-\r
- .code\r
-\r
-;------------------------------------------------------------------------------\r
-; _SmiExceptionEntryPoints is the collection of exception entry points followed\r
-; by a common exception handler.\r
-;\r
-; Stack frame would be as follows as specified in IA32 manuals:\r
-;\r
-; +---------------------+ <-- 16-byte aligned ensured by processor\r
-; + Old SS +\r
-; +---------------------+\r
-; + Old RSP +\r
-; +---------------------+\r
-; + RFlags +\r
-; +---------------------+\r
-; + CS +\r
-; +---------------------+\r
-; + RIP +\r
-; +---------------------+\r
-; + Error Code +\r
-; +---------------------+\r
-; + Vector Number +\r
-; +---------------------+\r
-; + RBP +\r
-; +---------------------+ <-- RBP, 16-byte aligned\r
-;\r
-; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT\r
-;------------------------------------------------------------------------------\r
-PageFaultIdtHandlerSmmProfile PROC\r
- push 0eh ; Page Fault\r
- test spl, 8 ; odd multiple of 8 => ErrCode present\r
- jnz @F\r
- push [rsp] ; duplicate INT# if no ErrCode\r
- mov qword ptr [rsp + 8], 0\r
-@@:\r
- push rbp\r
- mov rbp, rsp\r
-\r
- ;\r
- ; Since here the stack pointer is 16-byte aligned, so\r
- ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64\r
- ; is 16-byte aligned\r
- ;\r
-\r
-;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
-;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
- push r15\r
- push r14\r
- push r13\r
- push r12\r
- push r11\r
- push r10\r
- push r9\r
- push r8\r
- push rax\r
- push rcx\r
- push rdx\r
- push rbx\r
- push qword ptr [rbp + 48] ; RSP\r
- push qword ptr [rbp] ; RBP\r
- push rsi\r
- push rdi\r
-\r
-;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero\r
- movzx rax, word ptr [rbp + 56]\r
- push rax ; for ss\r
- movzx rax, word ptr [rbp + 32]\r
- push rax ; for cs\r
- mov rax, ds\r
- push rax\r
- mov rax, es\r
- push rax\r
- mov rax, fs\r
- push rax\r
- mov rax, gs\r
- push rax\r
-\r
-;; UINT64 Rip;\r
- push qword ptr [rbp + 24]\r
-\r
-;; UINT64 Gdtr[2], Idtr[2];\r
- sub rsp, 16\r
- sidt fword ptr [rsp]\r
- sub rsp, 16\r
- sgdt fword ptr [rsp]\r
-\r
-;; UINT64 Ldtr, Tr;\r
- xor rax, rax\r
- str ax\r
- push rax\r
- sldt ax\r
- push rax\r
-\r
-;; UINT64 RFlags;\r
- push qword ptr [rbp + 40]\r
-\r
-;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
- mov rax, cr8\r
- push rax\r
- mov rax, cr4\r
- or rax, 208h\r
- mov cr4, rax\r
- push rax\r
- mov rax, cr3\r
- push rax\r
- mov rax, cr2\r
- push rax\r
- xor rax, rax\r
- push rax\r
- mov rax, cr0\r
- push rax\r
-\r
-;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- mov rax, dr7\r
- push rax\r
- mov rax, dr6\r
- push rax\r
- mov rax, dr3\r
- push rax\r
- mov rax, dr2\r
- push rax\r
- mov rax, dr1\r
- push rax\r
- mov rax, dr0\r
- push rax\r
-\r
-;; FX_SAVE_STATE_X64 FxSaveState;\r
-\r
- sub rsp, 512\r
- mov rdi, rsp\r
- db 0fh, 0aeh, 00000111y ;fxsave [rdi]\r
-\r
-; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear\r
- cld\r
-\r
-;; UINT32 ExceptionData;\r
- push qword ptr [rbp + 16]\r
-\r
-;; call into exception handler\r
- mov rcx, [rbp + 8]\r
- mov rax, SmiPFHandler\r
-\r
-;; Prepare parameter and call\r
- mov rdx, rsp\r
- ;\r
- ; Per X64 calling convention, allocate maximum parameter stack space\r
- ; and make sure RSP is 16-byte aligned\r
- ;\r
- sub rsp, 4 * 8 + 8\r
- call rax\r
- add rsp, 4 * 8 + 8\r
- jmp @F\r
-\r
-@@:\r
-;; UINT64 ExceptionData;\r
- add rsp, 8\r
-\r
-;; FX_SAVE_STATE_X64 FxSaveState;\r
-\r
- mov rsi, rsp\r
- db 0fh, 0aeh, 00001110y ; fxrstor [rsi]\r
- add rsp, 512\r
-\r
-;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
-;; Skip restoration of DRx registers to support debuggers\r
-;; that set breakpoints in interrupt/exception context\r
- add rsp, 8 * 6\r
-\r
-;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
- pop rax\r
- mov cr0, rax\r
- add rsp, 8 ; not for Cr1\r
- pop rax\r
- mov cr2, rax\r
- pop rax\r
- mov cr3, rax\r
- pop rax\r
- mov cr4, rax\r
- pop rax\r
- mov cr8, rax\r
-\r
-;; UINT64 RFlags;\r
- pop qword ptr [rbp + 40]\r
-\r
-;; UINT64 Ldtr, Tr;\r
-;; UINT64 Gdtr[2], Idtr[2];\r
-;; Best not let anyone mess with these particular registers...\r
- add rsp, 48\r
-\r
-;; UINT64 Rip;\r
- pop qword ptr [rbp + 24]\r
-\r
-;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;\r
- pop rax\r
- ; mov gs, rax ; not for gs\r
- pop rax\r
- ; mov fs, rax ; not for fs\r
- ; (X64 will not use fs and gs, so we do not restore it)\r
- pop rax\r
- mov es, rax\r
- pop rax\r
- mov ds, rax\r
- pop qword ptr [rbp + 32] ; for cs\r
- pop qword ptr [rbp + 56] ; for ss\r
-\r
-;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
-;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
- pop rdi\r
- pop rsi\r
- add rsp, 8 ; not for rbp\r
- pop qword ptr [rbp + 48] ; for rsp\r
- pop rbx\r
- pop rdx\r
- pop rcx\r
- pop rax\r
- pop r8\r
- pop r9\r
- pop r10\r
- pop r11\r
- pop r12\r
- pop r13\r
- pop r14\r
- pop r15\r
-\r
- mov rsp, rbp\r
-\r
-; Enable TF bit after page fault handler runs\r
- bts dword ptr [rsp + 40], 8 ;RFLAGS\r
-\r
- pop rbp\r
- add rsp, 16 ; skip INT# & ErrCode\r
- iretq\r
-PageFaultIdtHandlerSmmProfile ENDP\r
-\r
- END\r
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